NewbieQ - WARNING:Xst:646 - Signal <next_outclock> is assign

[Jim Wang]

Can anyone suss why I get this warning from XST when "next_outclock" really
is being used on the next-to-last line? How can I silence it and win a
green check mark instead of a yellow !-point ?

This is with Xilinx ISE 6.2.03i (not the Webpack).

Thanks !

jimwang at cal dot berkeley dot edu

module cntr_50Mto10 (outclock, inclock);
output outclock;
input inclock;
reg outclock;

integer counter;
reg next_outclock;

always @ (negedge inclock) begin
if (counter == 5000000)
counter &lt;= 0;
else
counter &lt;= counter + 1;
end

always @ (posedge inclock) begin
if (counter &lt; 2500000)
next_outclock = 1;
else
next_outclock = 0;

outclock &lt;= next_outclock;
end
endmodule

 

[Jim Wu]

"Jim Wang" &lt;jim@may.sd.cox.net&gt; wrote in message
news:m3zmvqfkgk.fsf@may.sd.cox.net...

Can anyone suss why I get this warning from XST when "next_outclock"
really
is being used on the next-to-last line? How can I silence it and win a
green check mark instead of a yellow !-point ?

The warning message may not point out what exactly the problem is, but it
indicates there could be a prolem with your coding on next_outclock. You
mixed blocking and nonblocking assignments in the last "always" block. This
is not wrong, but you may get unexpected behavior.

HTH,
Jim
jimwu88NOOOSPAM@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips

This is with Xilinx ISE 6.2.03i (not the Webpack).

Thanks !

jimwang at cal dot berkeley dot edu

module cntr_50Mto10 (outclock, inclock);
output outclock;
input inclock;
reg outclock;

integer counter;
reg next_outclock;

always @ (negedge inclock) begin
if (counter == 5000000)
counter &lt;= 0;
else
counter &lt;= counter + 1;
end

always @ (posedge inclock) begin
if (counter &lt; 2500000)
next_outclock = 1;
else
next_outclock = 0;

outclock &lt;= next_outclock;
end
endmodule

 

Thanks!

I changed the assigments to non-blocking and the warning message went
away. I see I'll have to learn to properly interpret the Xilinx messages,
and they're not always obvious.

The warning message may not point out what exactly the problem is, but it
indicates there could be a prolem with your coding on next_outclock. You
mixed blocking and nonblocking assignments in the last "always" block. This
is not wrong, but you may get unexpected behavior.

HTH,
Jim
jimwu88NOOOSPAM@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips

always @ (posedge inclock) begin
if (counter &lt; 2500000)
next_outclock = 1;
else
next_outclock = 0;

outclock &lt;= next_outclock;
end

 

[Acceed See]

No, when you are well versed in Verilog coding, you can safely ignore most
warnings in XST.




&lt;jim@may.sd.cox.net&gt; wrote in message
news:u1x8zfp60.fsf@MAY.i-did-not-set--mail-host-address--so-shoot-me...

Thanks!

I changed the assigments to non-blocking and the warning message went
away. I see I'll have to learn to properly interpret the Xilinx messages,
and they're not always obvious.

The warning message may not point out what exactly the problem is, but it
indicates there could be a prolem with your coding on next_outclock. You
mixed blocking and nonblocking assignments in the last "always" block.
This
is not wrong, but you may get unexpected behavior.

HTH,
Jim
jimwu88NOOOSPAM@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips


always @ (posedge inclock) begin
if (counter &lt; 2500000)
next_outclock = 1;
else
next_outclock = 0;

outclock &lt;= next_outclock;
end