Newbie Xilinx Question: How to keep past designs?

[Brad Smallridge]

So you have a pretty good design and you want to save it, start another
design. How to do that? I clicked on New Design, new directory, went thru
the wizard, pasted the source form the old design into the new, (perhaps the
name should be something generic like mydesign and the design name or idea
is reflected in the directory), pasted the old constraint file into the new
constraint file, (is there anything else?), and started anew. Is there a
faster way of doing this?

 

[kpatel -at- xilinx -dot-]

Brad,

If you are using the Xilinx ISE tool, there are two methods you can use,
depending on exactly what you are trying to accomplish:

1. If you are looking to create a new project with the same sources in
a different location you can use the "File -> Save Project As" command
found under the File Menu.
2. If you are looking to capture the state of the project as it
currently stands, and do not want a new project, you can use the
Snapshot feature of ISE.

Both items are explained in more detail in the ISE Help Contents, which
you can access under the Help Menu from ISE.

Hope this helps.

Regards,
Kamal Patel
Xilinx Apps

Brad Smallridge wrote:

So you have a pretty good design and you want to save it, start another
design. How to do that? I clicked on New Design, new directory, went thru
the wizard, pasted the source form the old design into the new, (perhaps the
name should be something generic like mydesign and the design name or idea
is reflected in the directory), pasted the old constraint file into the new
constraint file, (is there anything else?), and started anew. Is there a
faster way of doing this?

 

[nick]

"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:<10hgkcgas2ais1f@corp.supernews.com>...

So you have a pretty good design and you want to save it, start another

my base design for 1000 series chips works, added a freecore and it works

now ported to Spartan - base design works but adding the freecore
causes base design not to work (not to mention freecore)

looked at timing constraints no problems.
????