newbie with Verilog and CPLD

[RF]

Hello,

I am new to Verilog and CPLD.

I want to make a VGA signal generator. I have made some code. I have
no errors at Xilinx Webpack 4.2 compiler, but I am not sure if the
FSM I have writted is working correctly.

Please, give me some suggestions on my code.

Best regards,

---
http://www.terra.es/personal9/listaco/VGAsignal.html


Here goes:
======================================================================
/*
* VGA 800x600 @ 60 Hz Signal Generator using Verilog
* ==================================================
*
* Date: 25 November 2004
*
* Intended CPLD: Xilinx XC9536XL (or XC9572XL)
* Clock source: 40 Mhz (25 nanoseconds per pixel)
* Posted on comp.lang.verilog and es.ciencia.electronica
*

Timing diagrams:
================

(For more detailed information on timing, see:

http://www.epanorama.net/documents/pc/vga_timing.html)

A) Horizontal Line:
===================

A1 ---> 800 pixels (20 us) Horizontal active display
A2 ---> 40 pixels ( 1 us) Horizontal front porch
A3 ---> 128 pixels ( 3.2 us) Horizontal Sync.
A4 ---> 88 pixels ( 2.2 us) Horizontal back porch
==================================================
1056 pixels (26.4 us) Total Horizontal line (about 37.879 KHz)

B) Vertical timing:
===================

(A1+A2+A3+A4) * 600 lines --> (15840 us) Vertical active display
B (1 line) ----------------> ( 26.4 us) Vertical front porch
C (4 lines) ---------------> ( 105.6 us) Vertical Sync.
D (23 lines) ---------------> ( 607.2 us) Vertical back porch
=====================================
16579.2 us Total VGA Frame (about 60.31 Hz)

*/


module VGAsignal (clock, reset, RGB, Hsync, Vsync);

input clock;
input reset;
output RGB, Hsync, Vsync;
reg RGB, Hsync, Vsync;

reg [10:0] Xcounter; // 2^11 = 2048
reg [9:0] Ycounter; // 2^10 = 1024

parameter A1=0, A2=1, A3=2, A4=3, B=4, C=5, D=6;

reg [2:0] CurrentState, NextState;


always @(Xcounter or Ycounter or CurrentState) // Next state logic
begin
NextState = A1;
case (CurrentState)
A1 : begin
if (Xcounter == 800) NextState = A2;
else NextState = A1;
end
A2 : begin
if (Xcounter == 840) NextState = A3;
else NextState = A2;
end
A3 : begin
if (Xcounter == 968) NextState = A4;
else NextState = A3;
end
A4 : begin
if ((Xcounter == 1056) & (Ycounter == 600)) NextState = B;
else NextState = A4;
end
B : begin
if (Ycounter == 602) NextState = C;
else NextState = B;
end
C : begin
if (Ycounter == 606) NextState = D;
else NextState = C;
end
D : begin
if (Ycounter == 628) NextState = A1;
else NextState = D;
end
endcase
end


always @(posedge clock or posedge reset) // Current state logic
begin
if (reset)
begin
CurrentState = A1;
Xcounter = 0;
Xcounter = 0;
end
else
begin
CurrentState = NextState;
if (Xcounter == 1057) Xcounter = 0;
else Xcounter = Xcounter + 1;
if (Ycounter == 629) Ycounter = 0;
else Ycounter = Ycounter + 1;
end
end


always @(CurrentState) // Output logic
begin
case (CurrentState)
A1 : begin
RGB = 1; Hsync = 0; Vsync = 0; // Active RGB
end
A2 : begin
RGB = 0; Hsync = 0; Vsync = 0; // Horizontal Front Porch
end
A3 : begin
RGB = 0; Hsync = 1; Vsync = 0; // Horizontal Sync.
end
A4 : begin
RGB = 0; Hsync = 0; Vsync = 0; // Horizontal Back Porch
end
B : begin
RGB = 0; Hsync = 0; Vsync = 0; // Vertical Front Porch
end
C : begin
RGB = 0; Hsync = 0; Vsync = 1; // Vertical Sync.
end
D : begin
RGB = 0; Hsync = 0; Vsync = 0; // Vertical Back Porch
end
default: begin
RGB = 0; Hsync = 0; Vsync = 0; // Is this needed?
end
endcase
end

endmodule