R
RadioXilinx
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I am new to FPGA and am using a Xilinx Virtix II 3000.
I created a simple loop using an ADC and a DAC and made the bitfile in Xilinx ISE. However when I load it, it does not run. I don't really know where to look for the problem.
Any ideas would be greatly appreciated!
Thanks
Jonathan
I created a simple loop using an ADC and a DAC and made the bitfile in Xilinx ISE. However when I load it, it does not run. I don't really know where to look for the problem.
Any ideas would be greatly appreciated!
Thanks
Jonathan