Newbie verilog question

[Tobias Weingartner]

This does not seem to want to be accepted by my verilog system.
The output declaration complains and does not seem to recognize
the << operator. Is the following legal? Any other way to do
this?

module decoder(enable,num,out);
parameter DBW = 1;
input enable; // Enable decoder output
input [DBW-1:0] num; // Line to enable
output [((1<<DBW)-1):0] out; // Output lines

assign out = (enable)?(1<<num):0;
endmodule


Thanks much for suggestions,

--
[100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax

 

It is legal. It compiles in both simulators I have available.

Assuming that you can't get this bug in your tools fixed,
you could try some workarounds. You might try defining
another parameter with the value (1<<DBW), and
substituting that in the declaration. This does carry
the risk that someone could override the value of this
derived parameter by mistake. Verilog-2001 has
localparams for this purpose, but your tools are
having enough trouble just with Verilog-1995.

 

sharp@cadence.com wrote:

It is legal. It compiles in both simulators I have available.

Assuming that you can't get this bug in your tools fixed,
you could try some workarounds. You might try defining
another parameter with the value (1<<DBW), and
substituting that in the declaration. This does carry
the risk that someone could override the value of this
derived parameter by mistake. Verilog-2001 has
localparams for this purpose, but your tools are
having enough trouble just with Verilog-1995.

I would think it's the second use of the << operator that
gives the problem. The first instance is shifting by a
constant. In the second case, shifting by num, there could
be some issue if you're trying to synthesize?

 

gabor@alacron.com wrote:

sharp@cadence.com wrote:
It is legal. It compiles in both simulators I have available.

Assuming that you can't get this bug in your tools fixed,
you could try some workarounds. You might try defining
another parameter with the value (1<<DBW), and
substituting that in the declaration. This does carry
the risk that someone could override the value of this
derived parameter by mistake. Verilog-2001 has
localparams for this purpose, but your tools are
having enough trouble just with Verilog-1995.

I would think it's the second use of the << operator that
gives the problem. The first instance is shifting by a
constant. In the second case, shifting by num, there could
be some issue if you're trying to synthesize?

I tried synthesizing with Xilinx ISE 6.1 and it works O.K.