Newbie Verilog ques: generate/endgenerate

[Steven Sharp]

"Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message news:<bkcr4m$55b$1$8302bc10@news.demon.co.uk>...

In reality, though, interesting modules have vector ports
and you can't connect up vector ports in a sensible way
on an instance-array member, because Verilog-95 has no
2-dimensional arrays of nets.

That isn't a requirement. There is a mechanism for connecting
vector ports to subsections of a wide vector instead. This is
somewhat clumsy, but it does provide an adequate way of connecting
up vector ports.

Oddly enough, while V2001 adds 2-dimensional arrays of nets,
instance arrays were not extended to allow connecting to them. I
think this got overlooked in the excitement over generates. I
have already proposed fixing it.

Nor does it have the
V2001 [lsb+:width] scheme for selecting a fixed-width
fragment of a bus. On the other hand, V2001 generate
sorts out this problem easily.

The capabilities of generates are a superset of the capabilities
of instance arrays. But in many cases, instance arrays are
sufficient. For those cases, their syntax is more concise than
generates. They are also more likely to be available in tools,
since they have been around longer and have fewer of the
implementation problems of Verilog generates.