Newbie Verilog ques: generate/endgenerate

[Sumanta Guha]

Hi:
I want to code up a realistically large memory unit with
registers made of D-flipflops.

The Palnitkar book is my main reference and the D-flipflop
code I can get there. And I see in Ch. 7 he discusses
the generate/endgenerate construct which I see as the way
to save on typing in all of the flipflops by hand - seems
basically generate/endgenerate is code to generate code
before simulation.

However, neither the veridos compiler nor the trial version
of Synapticad's Verilogger Pro seem to support generate/endgenerate.
We're in an academic environment here and don't have access
to any fancy (=expensive) tools!

Any solutions or suggestions for work-arounds will be highly appreciated.
Thanks much,
Sumanta Guha
Asiant Institute of Technology

 

[Steven Sharp]

guha@ait.ac.th (Sumanta Guha) wrote in message news:<94ed2a05.0309162307.73cf13ca@posting.google.com>...

However, neither the veridos compiler nor the trial version
of Synapticad's Verilogger Pro seem to support generate/endgenerate.
We're in an academic environment here and don't have access
to any fancy (=expensive) tools!

There is an older feature, arrays of instances, that might provide
what you need. They were added in Verilog-1995. However, most
tools didn't start implementing those until they started on the
Verilog-2001 extensions, which included generates. So those may
not be supported in your tools either.

You can write a program in some programming language (including
Verilog) which will generate source files with your desired
pattern. I believe that there is a preprocessor, vpp, that is
available and might be able to do this.

Or you can recognize that this isn't how designers write models
for memories, and use a more reasonable approach.

 

[Cliff Cummings]

Hi, Sumanta -

guha@ait.ac.th (Sumanta Guha) wrote in message news:<94ed2a05.0309162307.73cf13ca@posting.google.com>...

Hi:
I want to code up a realistically large memory unit with
registers made of D-flipflops.

Did you know you can declare arrays to model memories?

reg [7:0] mem [1:1023]; // 8-bit words x 1024 deep

and then access the array words using commands such as:

assign data = en ? mem[addr] : 8'bz;

The Palnitkar book is my main reference and the D-flipflop
code I can get there. And I see in Ch. 7 he discusses
the generate/endgenerate construct which I see as the way
to save on typing in all of the flipflops by hand - seems
basically generate/endgenerate is code to generate code
before simulation.

It would be useful to show the example in this forum. I do not have
Samir's 2nd edition yet (I reviewed his book - it is very good - and
he still owes me a copy - are you reading this, Samir??

NOTE: most designers that are trying to use a generate statement would
be better off using the Verilog-1995 array of instance construct. I
always give the guideline: think array-of-instance first, think
generate statements second. Since engineers are aware of VHDL generate
statements, they tend to think generates first - a mistake when coding
with Verilog.

The array of instance is better supported by most Verilog tools, and
has been since about 1998.

Example (untested - Verilog-2001 style module headers):

module myreg8 (output [7:0] dataout,
input [7:0] datain,
input clk, rst_n);

myreg r[7:0] (.q(dataout), .d(datain), .clk(clk), .rst_n(rst_n));
endmodule

module myreg (output reg q, input d, clk, rst_n);

always @(posedge clk or negedge rst_n)
if (!rst_n) q <= 0;
else q <= d;
endmodule

Works with most simulators (I can't speak for the simulators you have
mentioned).

However, neither the veridos compiler nor the trial version
of Synapticad's Verilogger Pro seem to support generate/endgenerate.
We're in an academic environment here and don't have access
to any fancy (=expensive) tools!

Any solutions or suggestions for work-arounds will be highly appreciated.
Thanks much,
Sumanta Guha
Asiant Institute of Technology

If you are unfamiliar with recommended Verilog coding practices, you
may want to go to my web page and download a few papers:
www.sunburst-design.com/papers

Regards - Cliff Cummings

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
Verilog On-Site Training Sale - 4-day Courses for $1,200/Student
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training

 

[John Providenza]

Cliff points out the straight forward way of creating memory
structures in Verilog. One thing that's not obvious is that
you can't select down to the bit level of the memory, ie, you
can't double index into it.

Thus:
reg [7:0] memory[1023:0];
creates a 1KByte memory array that you can only access by bytes.

There is no <compact> way to access a single bit. If you wanted
to retrieve a single bit, you need to access the byte 1st, then
select the bit you want from the byte. Likewise, you can't write
a single bit into this memory - you need to write the entire byte
UNLESS you do a read-modify-write type operation.

So, in general, this is a great way to create memory in Verilog,
just be aware of the limits!

John Providenza


cliffc@sunburst-design.com (Cliff Cummings) wrote in message news:<7788812d.0309170959.62761e1c@posting.google.com>...

Hi, Sumanta -

guha@ait.ac.th (Sumanta Guha) wrote in message news:<94ed2a05.0309162307.73cf13ca@posting.google.com>...
Hi:
I want to code up a realistically large memory unit with
registers made of D-flipflops.

Did you know you can declare arrays to model memories?

reg [7:0] mem [1:1023]; // 8-bit words x 1024 deep

and then access the array words using commands such as:

assign data = en ? mem[addr] : 8'bz;

The Palnitkar book is my main reference and the D-flipflop
code I can get there. And I see in Ch. 7 he discusses
the generate/endgenerate construct which I see as the way
to save on typing in all of the flipflops by hand - seems
basically generate/endgenerate is code to generate code
before simulation.

It would be useful to show the example in this forum. I do not have
Samir's 2nd edition yet (I reviewed his book - it is very good - and
he still owes me a copy - are you reading this, Samir??

NOTE: most designers that are trying to use a generate statement would
be better off using the Verilog-1995 array of instance construct. I
always give the guideline: think array-of-instance first, think
generate statements second. Since engineers are aware of VHDL generate
statements, they tend to think generates first - a mistake when coding
with Verilog.

The array of instance is better supported by most Verilog tools, and
has been since about 1998.

Example (untested - Verilog-2001 style module headers):

module myreg8 (output [7:0] dataout,
input [7:0] datain,
input clk, rst_n);

myreg r[7:0] (.q(dataout), .d(datain), .clk(clk), .rst_n(rst_n));
endmodule

module myreg (output reg q, input d, clk, rst_n);

always @(posedge clk or negedge rst_n)
if (!rst_n) q <= 0;
else q <= d;
endmodule

Works with most simulators (I can't speak for the simulators you have
mentioned).

However, neither the veridos compiler nor the trial version
of Synapticad's Verilogger Pro seem to support generate/endgenerate.
We're in an academic environment here and don't have access
to any fancy (=expensive) tools!

Any solutions or suggestions for work-arounds will be highly appreciated.
Thanks much,
Sumanta Guha
Asiant Institute of Technology

If you are unfamiliar with recommended Verilog coding practices, you
may want to go to my web page and download a few papers:
www.sunburst-design.com/papers

Regards - Cliff Cummings

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
Verilog On-Site Training Sale - 4-day Courses for $1,200/Student
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training

 

[Jonathan Bromley]

"Cliff Cummings" <cliffc@sunburst-design.com> wrote in
message news:7788812d.0309170959.62761e1c@posting.google.com...

NOTE: most designers that are trying to use a generate statement would
be better off using the Verilog-1995 array of instance construct.
Example (untested - Verilog-2001 style module headers):
[ Snip an example in which the instances have only scalar ports ]

I suspect I'm "allowing my VHDL undies to show" (as I was
accused by someone else here, a year or so ago) but I
really don't understand this position. Arrays of instances
are fine so long as every port on each instance is a scalar
connected to the relevant bit of a 1-dimensional vector.
In reality, though, interesting modules have vector ports
and you can't connect up vector ports in a sensible way
on an instance-array member, because Verilog-95 has no
2-dimensional arrays of nets. Nor does it have the
V2001 [lsb+:width] scheme for selecting a fixed-width
fragment of a bus. On the other hand, V2001 generate
sorts out this problem easily.

Please put me straight if I've got the wrong end of the
stick here, but I've always been of the opinion that
arrays of instances were as useful as a chocolate
teapot in the absence of 2-dimensional arrays of nets.
--
Jonathan Bromley, Consultant

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[David Jones]

In article <349ef8f4.0309180715.1c029ff9@posting.google.com>,
John Providenza <johnp3+nospam@probo.com> wrote:

Cliff points out the straight forward way of creating memory
structures in Verilog. One thing that's not obvious is that
you can't select down to the bit level of the memory, ie, you
can't double index into it.

Thus:
reg [7:0] memory[1023:0];
creates a 1KByte memory array that you can only access by bytes.

There is no <compact> way to access a single bit. If you wanted
to retrieve a single bit, you need to access the byte 1st, then
select the bit you want from the byte. Likewise, you can't write
a single bit into this memory - you need to write the entire byte
UNLESS you do a read-modify-write type operation.

Although true for Verilog-95, this is no longer true for Verilog-2001.
See p. 55 of IEEE 1364-2001.