B
(beta-) Frank Nitzsche
Guest
Hello @all,
at power-up, are all registers (for counters) initialized with known state
(e.g. zeros)?
Because the interface to a MC looks like a SRAM and there is no need for
reset. Moreover on the FPGA is not another unused pin for reset-input
available. All processes would be well syncronized forever, if they starts
with zeros. Internal timebase delivers a quarz-oszillator.
I hope, this text is sufficient understandable;-) Thanks!
Frank
at power-up, are all registers (for counters) initialized with known state
(e.g. zeros)?
Because the interface to a MC looks like a SRAM and there is no need for
reset. Moreover on the FPGA is not another unused pin for reset-input
available. All processes would be well syncronized forever, if they starts
with zeros. Internal timebase delivers a quarz-oszillator.
I hope, this text is sufficient understandable;-) Thanks!
Frank