Newbie questions re timing analysis

[Jules]

Hi,

I'm new to verilog and hardware description languages in general, and
am wondering about a few things. It seems all the FAQs I can find (the
old FAQ for this group and the "Alternate" FAQ) are rather out of date,
so don't seem to cover what I want to do. I'm a hobbyist, and don't
have a huge amount of spare cash, so being able to do this with free
tools is essential.

My main concerns at the moment are about timing analysis. If I'm
working at register transfer level, how do I determine (for a given
target technology whose switching time parameters are well known) how
long it will take for an output to settle (and hence calculate the
fastest speed I can clock my circuit at)?

One of the tools I'm working with, Icarus Verilog, provides output in
EDIF format. What tools are available to take this and allow me to
view it in a schematic format? Again, free tools are preferred.

I have access to both Windows & Linux, so tools for either platform
will suffice.

 

[Mike Treseler]

Jules wrote:

If I'm
working at register transfer level, how do I determine (for a given
target technology whose switching time parameters are well known) how
long it will take for an output to settle (and hence calculate the
fastest speed I can clock my circuit at)?

Run a full synthesis and check the static timing report.

One of the tools I'm working with, Icarus Verilog, provides output in
EDIF format. What tools are available to take this and allow me to
view it in a schematic format?

Both ise and quartus have RTL viewers that
require only source code.

-- Mike Treseler

 

[Jules]

Mike Treseler wrote:

Both ise and quartus have RTL viewers that
require only source code.

-- Mike Treseler

Thanks. I hadn't realised that either of these were available in free
editions; I'm currently downloading the free version of quartus to have
a play with.