Newbie question

[Stathis]

I am using Xilinx ISE.
I am developping some combinational components.
When i am using the "always @" feature to determine a level-sensitive
behaviour, the synthesized circuit contains latches. I assume this means
sequential logic is added to the component. Should i avoid this by using the
assign statement instead?

 

[Kim Hyun-Gyu]

If a latch is inferred in the synthesis phase, it caused by your RTL code.

if you use incomplete if-else or case state it infer latch to hold current
state.
check the coding guideline (likes RMM and the others..) then check your code

"Stathis" <stathisgotsis@hotmail.com> wrote in message
news:bo6rkq$27qb$1@ulysses.noc.ntua.gr...

I am using Xilinx ISE.
I am developping some combinational components.
When i am using the "always @" feature to determine a level-sensitive
behaviour, the synthesized circuit contains latches. I assume this means
sequential logic is added to the component. Should i avoid this by using
the
assign statement instead?

 

[John_H]

"Stathis" <stathisgotsis@hotmail.com> wrote in message
news:bo6rkq$27qb$1@ulysses.noc.ntua.gr...

I am using Xilinx ISE.
I am developping some combinational components.
When i am using the "always @" feature to determine a level-sensitive
behaviour, the synthesized circuit contains latches. I assume this means
sequential logic is added to the component. Should i avoid this by using
the
assign statement instead?

The trouble that your signals don't have all situations explicitly defined
so the "other" conditions result in the variable staying the same - a latch.

You can define the "other" states either explicitly in your statements
(if/else or case, for instance) or you can front-load your always block
using blocking operators.

wire [3:0] InSigs;
wire [1:0] OutSigs;
always @(InSigs)
begin
OutSigs = 0; /* front-loading with blocking operators supplies a way to
specify the OutSigs[0] else */
if( InSigs== 4'h5 | ~^InSigs ) OutSigs = 2'b10;
else OutSigs[1] = 1'b0; /* OutSigs[0] doesn't have an explicit
assignment in the else case */
end

 

[Stathis]

Thank you both for the help.
Where can i find some basic RTL coding guidelines like the one you told me
earlier...?

 

[Kim Hyun-Gyu]

You can buy the "Reuse Methodology Manual" by M. Keating and P. Bricaud(KAP)
from the book store.

Humm.. and some basic coding guidelines are presented by EDA vendor. (for
example "Synopsys Coding Guideline for Synthesis from SOLD and so on..)

and check VSIA or Openmore website..


"Stathis" <stathisgotsis@hotmail.com> wrote in message
news:bo9ljo$29u4$1@ulysses.noc.ntua.gr...

Thank you both for the help.
Where can i find some basic RTL coding guidelines like the one you told me
earlier...?

 

[VhdlCohen]

Thank you both for the help.
Where can i find some basic RTL coding guidelines like the one you told me

Also check CLiff's site:
http://www.sunburst-design.com/papers/

In addition, my book "Real Chip Design and Verification Using Verilog and VHDL"

provides severla styles for models and testbenches, along with differences
between VHDL and Verilog, which gets into a deeper understanding of the
languages.
Ben
----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Using PSL/SUGAR with Verilog and VHDL
Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------