Newbie question

[Thoma]

Hi,

I am new to verilog but have a good experience with vhdl.
How can I convert the following vhdl to verilog ?

signal ab : std_logic_vector(1 downto 0);
alias a : std_logic is ab(1);
alias b : std_logic is ab(0);

Thanks in advance

Thoma

 

[John_H]

Thoma wrote:

Hi,

I am new to verilog but have a good experience with vhdl.
How can I convert the following vhdl to verilog ?

signal ab : std_logic_vector(1 downto 0);
alias a : std_logic is ab(1);
alias b : std_logic is ab(0);

Thanks in advance

Thoma

Which Verilog? System Verilog has new functionality which might include
aliasing but Verilog 2001 and the original Verilog don't support aliasing.

The closest one could get in V2k might be by using macros:

`define a ab[0]

assign myVal = myCount + `a;
assign `a = myBit;

Not very convenient, but a workaround.

- John_H

 

[Thoma]

John_H a écrit :

Thoma wrote:
Hi,

I am new to verilog but have a good experience with vhdl.
How can I convert the following vhdl to verilog ?

signal ab : std_logic_vector(1 downto 0);
alias a : std_logic is ab(1);
alias b : std_logic is ab(0);

Thanks in advance

Thoma

Which Verilog? System Verilog has new functionality which might include
aliasing but Verilog 2001 and the original Verilog don't support aliasing.

The closest one could get in V2k might be by using macros:

`define a ab[0]

assign myVal = myCount + `a;
assign `a = myBit;

Not very convenient, but a workaround.

- John_H

Hi John,

I use Verilog 2001 so I am forced to use the macro workaround.

Thanks

Thoma

 

On Oct 18, 12:44 pm, John_H <newsgr...@johnhandwork.com> wrote:

Which Verilog?  System Verilog has new functionality which might include
aliasing but Verilog 2001 and the original Verilog don't support aliasing..

SystemVerilog does include an alias statement, but it is not needed.
You can already alias two signals together in Verilog. Use a module
with two ports that connect to the same signal inside, shorting the
two ports together. Here is a fairly general version:

module my_alias (.p1(a), .p2(a));
parameter width = 1;
inout [width-1:0] a;
endmodule

Now you can short together your signals with

my_alias a1(a, ab[1]);
my_alias a0(b, ab[0]);

Or do it all at once, making ab equivalent to the signals a and b
concatenated together:

my_alias #(2) a1({a,b}, ab);

Since the two ports have been given different external names, you can
use named connections:

my_alias #(.width(2)) a1(.p1({a,b}), .p2(ab));

Sometimes a simpler version of an aliasing module is used:

module my_alias (a,a);
inout a;
endmodule

This is legal, but looks suspicious and cannot be connected by port
names, since the ports do not have distinct external names.