newbie question

[Florian Student]

Dear Comp.lang.verilog,

I've been trying to write a simple free running 8 bit counter. Here's
the source I got so far:

// Module Declaration
module counter
(
clk, out
);
// Port Declaration
input clk;
output [7:0] out;
reg [7:0] counter;

always @(posedge clk)
begin
counter = counter + 1;
out = counter;
end

endmodule

The Quartus compiler tells me that there's an
"Error: Verilog HDL Procedural Assignment error at counter.v(21):
illegal Procedural Assignment to nonregister data type out"

What am I doing wrong?

Thanx in advance,

Florian

 

[Ensoul Chee]

the out port sould not be in always block.

always @(posedge clk)
begin
counter = counter + 1;
// out = counter;
end

assign out = counter;