Newbie Question: Unused pins in the constraint file

[Brad Smallridge]

When one is working on a development board one is often turning on parts of
the board and turning off other parts. So when I tried to shut down one
chip hanging off my Spartan 3 by basically doing nothing with its outputs I
got this NgdBuild:755 Could not find net(s) error and it would not generate.
It would seem to me if the synthesizer saw constraints not used in the
source VHDL, it should possibly give a warning, but should be able to
complete the design. PACE wouldn't open but I removed the outputs (that is:
the FPGA inputs) from the constraint file with the text editor. This is
remenisent of compilers that complain when a subroutine doesn't get called.
I would like to enter all my board design IOs into the constraint file
whether I use them or not.

Brad

 

[John Williams]

Hi Brad,

Brad Smallridge wrote:

It would seem to me if the synthesizer saw constraints not used in the
source VHDL, it should possibly give a warning, but should be able to
complete the design.

[snip]

I would like to enter all my board design IOs into the constraint file
whether I use them or not.

Indeed. I think you want to pass the -aul option to ngdbuild:

From `ngdbuild --help`:

-aul Allow unmatched LOC constraints

I'd like the inverse of this - the option to generate an error (not just
a warning) if there are unconstrained pins. On a development board with
lots of off-chip resources, randomly scattering unLOCd pins to the 4
winds can yield very unpredictable results! I ended up writing a little
awk script that parses the build log to see if the number of LOCd pins
matches the total number of pins in the design.

Cheers,

John