D
Durward
Guest
Hello,
I am using ISE Foundation 5.2i with a Spartan2 and am running into the
following problems:
1. I would like to utilize input/output pads to denote the FPGA I/Os.
I typically have been using Schematic Entry and then specify the
corresponding pins for the I/O Markers in "Assign Package Pins" (or
similar).
2. For this design, I would like to use a 32 bit input bus and 32 bits
of output. Rather than placing all 32 on my toplevel schematic, it
would be cleaner to use a macro to represent a 32 bit Input pad.
However, each time I create said macro with 32 I/O Markers going to a
bus, it results in a macro block with 32 input leads (one for each
marker). Is there a way to create a macro such that the leads only
show on the macro level schematic and the toplevel schematic just has
the macro form with desired bus32 output designator?
3. Is an IPAD (IOPAD,OPAD) of any benefit here? I see them mentioned
in the ISE5.2i Libraries Guide (IPAD-primitive,IPAD8-macro) but they
do not show up as a selectable part in "Select Part-> I/O' of the
Schematic utility. Why?
4. Can PACE (Pinout and Constraints Editor) be used to achieve this by
creating a UCF for the lowlevel macro? Or is FPGA Editor-> "Add Macro
External Pin" better?
Thank you for any help you can provide.
Durward
I am using ISE Foundation 5.2i with a Spartan2 and am running into the
following problems:
1. I would like to utilize input/output pads to denote the FPGA I/Os.
I typically have been using Schematic Entry and then specify the
corresponding pins for the I/O Markers in "Assign Package Pins" (or
similar).
2. For this design, I would like to use a 32 bit input bus and 32 bits
of output. Rather than placing all 32 on my toplevel schematic, it
would be cleaner to use a macro to represent a 32 bit Input pad.
However, each time I create said macro with 32 I/O Markers going to a
bus, it results in a macro block with 32 input leads (one for each
marker). Is there a way to create a macro such that the leads only
show on the macro level schematic and the toplevel schematic just has
the macro form with desired bus32 output designator?
3. Is an IPAD (IOPAD,OPAD) of any benefit here? I see them mentioned
in the ISE5.2i Libraries Guide (IPAD-primitive,IPAD8-macro) but they
do not show up as a selectable part in "Select Part-> I/O' of the
Schematic utility. Why?
4. Can PACE (Pinout and Constraints Editor) be used to achieve this by
creating a UCF for the lowlevel macro? Or is FPGA Editor-> "Add Macro
External Pin" better?
Thank you for any help you can provide.
Durward