Newbie Question on State Machines

  • Thread starter jjlindula@hotmail.com
  • Start date
J

jjlindula@hotmail.com

Guest
Hello, I'm excited to be learning Verilog and have a few books to get
me started but I do have one question that I hope someone can answer.
I'll give a little code:

module(input Y, output Z)

reg X;
reg A, B;

always @(posedge clk_in)
if(reset)begin
A = 0;
B = 0;
X = 0;
end

else
case(my_stateMachine_reg)
1: if(Y)
X = 1;
else
X = 0;
2: A = 1;
3: B =0;
endcase

My question is, in states 2 and 3 do I need to have X = 0?
Should my code look like:

module(input Y, output Z)

reg X;
reg A, B;

always @(posedge clk_in)
if(reset)begin
A = 0;
B = 0;
X = 0;
else
case(my_stateMachine_reg)
1: begin
A = 0;
B = 0;
if(Y)begin
X = 1;
else
X = 0;
end
2: A = 1;
B = 0;
X = 0;

3: B =0;
A = 0;
X = 0;
endcase


Do I really need to include each reg variable in each state and give
it a value?
thanks,
joe
 
On Thu, 27 Mar 2008 07:20:22 -0700 (PDT),
<jjlindula@hotmail.com> wrote:

Hello, I'm excited to be learning Verilog and have a few books to get
me started but I do have one question that I hope someone can answer.
I'll give a little code:
snip
My question is, in states 2 and 3 do I need to have X = 0?
Click to expand...
No. You're updating X synchronously, so it will be stored
in a flipflop. Consequently, it's OK for X to hold its
value across a clock cycle.

In COMBINATIONAL always blocks, it's essential to assign
to every variable on every pass through the block. But
your code is synchronous [always @(posedge clock}]
so this concern does not apply.

However, you ARE doing a Bad Thing: variables A, B, X are
declared at the top level of the module and therefore are
visible to every always block in the module; consequently,
it's essential for you to update them using NONBLOCKING
assignment (<=) in any clocked always block. Get this
wrong and you will have all manner of mystery simulation
problems. You MUST fix it. In a clocked always block,
ANY variable that is visible outside the block MUST
be written using nonblocking assignment.

Also, there seems to be no declaration of my_stateMachine_reg
in your code - I guess that's because you've edited the
example before posting it here.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
On Mar 27, 4:09 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
On Thu, 27 Mar 2008 07:20:22 -0700 (PDT),



jjlind...@hotmail.com> wrote:
Hello, I'm excited to be learning Verilog and have a few books to get
me started but I do have one question that I hope someone can answer.
I'll give a little code:
snip
My question is, in states 2 and 3 do I need to have X = 0?

No. You're updating X synchronously, so it will be stored
in a flipflop. Consequently, it's OK for X to hold its
value across a clock cycle.

In COMBINATIONAL always blocks, it's essential to assign
to every variable on every pass through the block. But
your code is synchronous [always @(posedge clock}]
so this concern does not apply.

However, you ARE doing a Bad Thing: variables A, B, X are
declared at the top level of the module and therefore are
visible to every always block in the module; consequently,
it's essential for you to update them using NONBLOCKING
assignment (<=) in any clocked always block. Get this
wrong and you will have all manner of mystery simulation
problems. You MUST fix it. In a clocked always block,
ANY variable that is visible outside the block MUST
be written using nonblocking assignment.

Also, there seems to be no declaration of my_stateMachine_reg
in your code - I guess that's because you've edited the
example before posting it here.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Click to expand...
Jonathan,

Hello, thanks for responding to my post it is very helpful. I can't
wait to master Verilog so I can start learning SystemVerilog.

Thanks,
joe
 
On Mar 27, 4:09 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
On Thu, 27 Mar 2008 07:20:22 -0700 (PDT),



jjlind...@hotmail.com> wrote:
Hello, I'm excited to be learning Verilog and have a few books to get
me started but I do have one question that I hope someone can answer.
I'll give a little code:
snip
My question is, in states 2 and 3 do I need to have X = 0?

No. You're updating X synchronously, so it will be stored
in a flipflop. Consequently, it's OK for X to hold its
value across a clock cycle.

In COMBINATIONAL always blocks, it's essential to assign
to every variable on every pass through the block. But
your code is synchronous [always @(posedge clock}]
so this concern does not apply.

However, you ARE doing a Bad Thing: variables A, B, X are
declared at the top level of the module and therefore are
visible to every always block in the module; consequently,
it's essential for you to update them using NONBLOCKING
assignment (<=) in any clocked always block. Get this
wrong and you will have all manner of mystery simulation
problems. You MUST fix it. In a clocked always block,
ANY variable that is visible outside the block MUST
be written using nonblocking assignment.

Also, there seems to be no declaration of my_stateMachine_reg
in your code - I guess that's because you've edited the
example before posting it here.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Click to expand...
Jonathan,

Hello, when you mention the reg variables being declared at the top of
the module I remember reading about how to declare local variables in
the always block but can remember how it was done. Is it something
like I have below? Thanks,
joe

module(input Y, output Z)



always @(posedge clk_in)
reg X;
reg A, B;
if(reset)begin
A = 0;
B = 0;
X = 0;
end

else
case(my_stateMachine_reg)
1: if(Y)
X = 1;
else
X = 0;
2: A = 1;
3: B =0;
endcase
 
On Apr 1, 5:30 pm, "jjlind...@hotmail.com" wrote:

Hello, when you mention the reg variables being declared at the top of
the module I remember reading about how to declare local variables in
the always block but can remember how it was done.
Click to expand...
Local variables can be declared in any NAMED begin...end block.
Something like this:

module .....;

reg Q, R; // module-level variables

always @(posedge clock) begin : block_name
reg B; // local variable
if (reset) begin
Q <= 0; // in clocked block, MUST write module-level
R <= 0; // vars using nonblocking assignment <=
B = 0; // but it's fine to write locals with blocking =
end else begin
// Clocked actions
B = <some complicated function of various inputs>;
// Local var B is already updated - we can use its
// new value straight away - no need to wait for a clock
if (polarity_control)
Q <= B;
else
Q <= ~B;
// But when I use Q below, its value has NOT yet been
// updated so the assignment to R will use the old,
// pre-clock version of Q
R <= Q;
end
end // block_name

"Local" variables in a block aren't really local at all.
First off, they're static - they are created and initialised
at the start of simulation, and they stick there for the life
of the simulation; they don't come and go dynamically in the
way that function local variables in C would do. Secondly,
they are globally visible; variable B in my example in fact
has the name "block_name.B" and can be accessed from outside
the block. But synthesis tools can't process these dotted
names, so your local variable is completely safe in
synthesisable (RTL) code.

HTH
--
Jonathan Bromley
 
On Apr 1, 7:15 pm, s...@oxfordbromley.plus.com wrote:
On Apr 1, 5:30 pm, "jjlind...@hotmail.com" wrote:

Hello, when you mention the reg variables being declared at the top of
the module I remember reading about how to declare local variables in
the always block but can remember how it was done.

Local variables can be declared in any NAMED begin...end block.
Something like this:

module .....;

reg Q, R; // module-level variables

always @(posedge clock) begin : block_name
reg B; // local variable
if (reset) begin
Q <= 0; // in clocked block, MUST write module-level
R <= 0; // vars using nonblocking assignment <=
B = 0; // but it's fine to write locals with blocking =
end else begin
// Clocked actions
B = <some complicated function of various inputs>;
// Local var B is already updated - we can use its
// new value straight away - no need to wait for a clock
if (polarity_control)
Q <= B;
else
Q <= ~B;
// But when I use Q below, its value has NOT yet been
// updated so the assignment to R will use the old,
// pre-clock version of Q
R <= Q;
end
end // block_name

"Local" variables in a block aren't really local at all.
First off, they're static - they are created and initialised
at the start of simulation, and they stick there for the life
of the simulation; they don't come and go dynamically in the
way that function local variables in C would do. Secondly,
they are globally visible; variable B in my example in fact
has the name "block_name.B" and can be accessed from outside
the block. But synthesis tools can't process these dotted
names, so your local variable is completely safe in
synthesisable (RTL) code.

HTH
--
Jonathan Bromley
Click to expand...
Jonathan,

Thank you very much for that example. I have a better understanding of
local 'static' variables.
joe
 
On 4/27/2011 9:49 PM, jjlindula@hotmail.com.remove-bn1-this wrote:

Hello, when you mention the reg variables being declared at the top of
the module I remember reading about how to declare local variables in
the always block but can remember how it was done. Is it something
like I have below? Thanks,
Click to expand...
You need to declare the variables inside a named block.

always @(posedge clk_in) begin : some_name
declare variables, etc.
end

One of the reasons for this is that you need to have a valid scope path
to the variable for VPI access or other out of scope references.

Cary
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top