Newbie question--> Obtaining RTL netlist from Xilinx ISE 6

[Mirembe]

I am trying to figure out if there is a way of obtaining the RTL
netlist in Project Navigator when I synthesize. The RTL schematic that
is obtained under 'synthesise option' on the other hand uses the
UNISIM library but for some reason I can only get the schematic (which
is read-only) and not the actual netlist code that uses the UNISIM
library.

I used the post-translate simulation model under the 'implement
design' option but that only gives me the netlist for simulation model
which uses the simulation primitives (SIMPRIMS library) which dont
represent the true implementation of the device.

I am currently using the ISE webpack 6.2i, the free version but
willing to upgrade to the full version if it provides this capability.