Newbie question IO pin and Spartan6

[eryer]

Hi,
i have two newbie questions:
is it possible to use differential pin as single ended pin?
is it possible to implement SPI in any IO pin?
thans

 

[Kim Povlsen]

Hi Eryer,

Simple answers:
Yes and yes.

On Fri, 15 Oct 2010 03:21:16 -0700 (PDT), eryer
<idkfaidkfaidkfa@gmail.com> wrote:

Hi,
i have two newbie questions:
is it possible to use differential pin as single ended pin?
is it possible to implement SPI in any IO pin?
thans

 

[eryer]

On 15 Ott, 12:42, Kim Povlsen <k...@rtldesign.dk> wrote:

Hi Eryer,

Simple answers:
Yes and yes.

On Fri, 15 Oct 2010 03:21:16 -0700 (PDT), eryer

idkfaidkfaid...@gmail.com> wrote:
Hi,
i have two newbie questions:
is it possible to use differential pin as single ended pin?
is it possible to implement SPI in any IO pin?
thans

Thanks for your answers....
from xilix ise, where can i find SPI logicore?I don't find it...

 

[Gabor]

On Oct 15, 7:25 am, eryer <idkfaidkfaid...@gmail.com> wrote:

On 15 Ott, 12:42, Kim Povlsen <k...@rtldesign.dk> wrote:

Hi Eryer,

Simple answers:
Yes and yes.

On Fri, 15 Oct 2010 03:21:16 -0700 (PDT), eryer

idkfaidkfaid...@gmail.com> wrote:
Hi,
i have two newbie questions:
is it possible to use differential pin as single ended pin?
is it possible to implement SPI in any IO pin?
thans

Thanks for your answers....
from xilix ise, where can i find SPI logicore?I don't find it...

I thought the only SPI "core" is the one for Microblaze which would be
in the EDK
rather than ISE. Also if you want to use SPI to configure the FPGA as
well as
using it to access a flash memory after configuration, you need to use
the
pins as described in the Configuration User Guide.

SPI itself is a fairly simple protocol, so normally people just write
their own interface if using a SPI device other than device
configuration
or use with an embedded processor. Generally the data sheet for
the SPI-connected device will show you the required protocol.

Regards,
Gabor

 

[Anssi Saari]

Gabor <gabor@alacron.com> writes:

I thought the only SPI "core" is the one for Microblaze which would
be in the EDK rather than ISE.

There's an SPI example for a Xilinx CPLD available somewhere on
Xilinx's website. I just remember it was mentioned in this group once.
Come to think of it, Altera has an SPI master available too, also in
their CPLD pages.

 

[Bryan]

All differential pins can be used as single-ended pins. See the
following from Xilinx Spartan-6 UG381:

Each IOB contains both input, output, and 3-state SelectIO drivers.
These drivers can be
configured to various I/O standards. Differential I/O uses the two
IOBs grouped together
in one tile.
• Single-ended I/O standards (LVCMOS, LVTTL, HSTL, SSTL, PCI)
• Differential I/O standards (LVDS, RSDS, TMDS, Differential HSTL and
SSTL)
• Differential and VREF dependent inputs are powered by VCCAUX
Each Spartan-6 FPGA I/O tile contains two IOBs, and also two ILOGIC
blocks and two
OLOGIC blocks

Bryan