Newbie Question Clocks on the Spartan 3

[Brad Smallridge]

Just got my Xilinx Spartan 3 board operational. One part of the board sends
digital data to a video DAC at 48 MHz. I did a priliminary program to send
a test pattern to this DAC but the results change with a modification to the
VGACLK'event and VGACLK='1' line. If I change the '1' to a '0' I get better
results. I suppose I should now go Spartan 3 specific and use the Xilinx
DCMs? Can someone point me to beginners doc on clock distribution and DCMs?
I am printing the 68 page XAPP462 as I write this post but sheesh what a
horse!

Thanks,

Brad

 

[rickman]

Brad Smallridge wrote:

Just got my Xilinx Spartan 3 board operational. One part of the board sends
digital data to a video DAC at 48 MHz. I did a priliminary program to send
a test pattern to this DAC but the results change with a modification to the
VGACLK'event and VGACLK='1' line. If I change the '1' to a '0' I get better
results. I suppose I should now go Spartan 3 specific and use the Xilinx
DCMs? Can someone point me to beginners doc on clock distribution and DCMs?
I am printing the 68 page XAPP462 as I write this post but sheesh what a
horse!

What do you mean "better results"? Sounds to me like you have a timing
issue between your data and clock. What is the timing relationship
between the two? Is the DAC clock feeding into the FPGA or out from the
FPGA? What edge of the clock is the DAC reading data on? What edge of
the clock is the FPGA sending the data on?

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Brad Smallridge]

It's running now. Not all my pins were soldered correctly.
And a timing variable was off to boot.
I may still want to use the DCM however.

To answer your questions:

What do you mean "better results"? Sounds to me like you have a timing
issue between your data and clock. What is the timing relationship
between the two?

Well right now I'm a happy camper.

Is the DAC clock feeding into the FPGA or out from the
FPGA?

An FAE suggested I run an outside clock to the FPGA and to the DAC.

What edge of the clock is the DAC reading data on?

Rising

What edge of
the clock is the FPGA sending the data on?

I switched it back to rising with this sort of VHDL:
if( VGACLK'event and VGACLK='1')

Thanks for your help.
What's with your web site?

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX