Newbie question. Allocators unsupported ?

I´ve tried to define a dynamic data structur in VHDL.
I´m using the Xilinx ISE Webpack 9.2.
During compilation I got the message "Allocatora unsupported".
What is the reason for this behaviour ?

library IEEE;
library STD;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;


entity enigma is
Port (input : in STD_LOGIC; output : out STD_LOGIC; mode : in
Bit);

-- The wheel type
type wheel_index is range 0 to 30;
type wheel_string is array (wheel_index'left to wheel_index'right) of
character;
type wheel_array is array (0 to 11) of wheel_string;

-- The rotor type
type rotor_type is
record
wheel_number : integer;
wheel : wheel_string;
start : character;
stepsize : integer;
position : integer;
end record;

-- The pointer to the rotor type
type rotor_pointer is access rotor_type;

-- The enigma type
type enigma_type is
record
chars : integer;
rotors : integer;
alphabet : wheel_string;
rotor : rotor_pointer;
end record;
-- This is the only global variable
-- Must be declared as "shared" to use it global
shared variable the_enigma : enigma_type;
end enigma;

Somewhere else in the programm.
This does not work.

-- Allocate memory for the rotors
the_enigma.rotor := new rotor_type;


Thank you for help

 

[Brian Drummond]

On Sat, 3 May 2008 19:01:04 -0700 (PDT), HansWernerMarschke@web.de wrote:

I´ve tried to define a dynamic data structur in VHDL.
I´m using the Xilinx ISE Webpack 9.2.
During compilation I got the message "Allocatora unsupported".
What is the reason for this behaviour ?

What gave you the message? The XST synthesis tool?

Allocators should be supported for simulation - in which your VHDL code is
executed as though it was software.

But for synthesis, you can't expect dynamic allocation to work ... you can't
decide, at run-time, my CPU or Enigma machine isn't big enough, I'll dynamically
allocate a new ALU or rotor...

Hence for synthesis, "new" and "deallocate" are out.
Hence also, access types (since you call them pointers, I guess you are coming
from a C background?) are out.

VHDL as a language requires a different discipline to C to keep things simple,
clean and general. (It's much better in many ways).

Hardware requires a different discipline to software; one aspect of this is that
resources must be created before run-time, then fixed in size. (That takes place
during the elaboration phase, after compilation)

I suggest a fixed-size array of rotors, in the enigma_type record. (This comes
from the hardware discipline).

To keep the solution general, make the number of rotors an integer constant, or
better still, a generic. Then you can write an Enigma which works with any
reasonable number of rotors, and fix the number at elaboration by filling in the
"generic". (This comes from the VHDL discipline).

entity enigma is
Generic (
rotor_count : in integer := 3 -- default is 3 rotors
)
Port (
input : in STD_LOGIC;
....
);

....
type rotor_array is array (1 to rotor_count) of rotor_type;
-- You can now safely forget what the array bounds are...

type enigma_type is
record
....
rotors : rotor_array;
end record;

Then to iterate over rotors in a process,
for i in rotors'range loop
-- loop over entire array, whatever its bounds are
....
end loop;

or to generate a process for each rotor in the architecture,
for i in rotors'range generate
....
end generate;

To instantiate the Enigma with n rotors, use a generic map to set rotor_count,
exactly like the port map wires up the I/O ports.

use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

Lose these two and use IEEE.numeric_std.all instead. They do work, sort of, but
store up problems to bite you later.

- Brian

 

Thank´s for your answer Brian.
I got the error by using "create schematic symbol" although I don´t
know what this exactly means.
Till know I´ve never done hardware programming. I only know some C, C+
+, ADA, PL1 and some other languages.
So what is the difference between simulation and synthesis ?
What are you allowed to do or which programm constructs can you use
and which not ?
Are dynamic data structures the only thing which is forbidden for
synthesis ?
I would be glad to have a running simulation and get some more
experience with the Xilinx ISE tool.
You can do a syntax check in Xilinx ISE. Is there also a check if the
code is ready for synthesis ?
Which steps in the design process can you use if you are only doing a
simulation ?
What is the better tool for simulation the Xilinx ISE simulator or the
Modelsim starter edition ?
What is the difference between the free Xilinx ISE Webpack edition and
the comercial edition ?
As I was told and I understood the only difference is that you can not
programm all FPGA's with the free edition ?
Ok. I will look into the tutorials for the Xilinx ISE.

 

[Brian Drummond]

On Sun, 4 May 2008 14:28:58 -0700 (PDT), HansWernerMarschke@web.de wrote:

Thank´s for your answer Brian.
I got the error by using "create schematic symbol" although I don´t
know what this exactly means.

It looks as if the Xilinx tools tested the entity at least partially for
synthesisability, when creating a schematic symbol for it. I can't help; I have
never used the Xilinx schematic level, just used VHDL from my top level
testbench downwards.

Till know I´ve never done hardware programming. I only know some C, C+
+, ADA, PL1 and some other languages.

Ada will help with the discipline of VHDL programming; none of these will help
with the discipline of hardware design. (A TTL databook, a soldering iron and a
wire-wrap gun were how I got started

So what is the difference between simulation and synthesis ?

Simulation is software execution. As a result it is dog slow, but you have
access to the full language, and anything goes. Its primary purpose is
verification of the hardware design.

A typical simulation program, aka "testbench" may have 4 components;
(1) the hardware design (which is written in the synthesisable subset of the
language)
(2) a "software style" model of the same design; written at the highest
practical level of abstraction, or possibly ported from a "C" or FORTRAN
original
(3) a stimulus generator, generating test inputs (or reading them from a file)
(4) a result checker, to verify that (a) the model generates the correct outputs
and (b) the hardware matches the model (but probably with some time delay) -
this can be done with a comparator, and ASSERT that the results are identical.

The simulator, in addition to executing this, provides comprehensive debuging
facilities, including display of waveforms on any signal inside the hardware.

Not all testbenches have all 4 elements; it is common to develop without (1)
until (2) accepts inputs from (3) and satisfies checker (4). Or for simpler
blocks, omit model (2).

Synthesis will ONLY accept (1) the hardware design, and convert it to an
equivalent form to (for us) download into an FPGA. You only synthesise for real,
once the design has passed simulation. (However it's good practice to synthesise
significant blocks of the design, to ensure they (a) are synthesisable, (b)
occupy reasonable resources, and (c) deliver approximately the speed you
require.

What are you allowed to do or which programm constructs can you use
and which not ?
For simulation : anything; you can use the full language to verify hardware

(e.g. read a .BMP file, simulate DCT, compression, coding etc, and write a .JPG
file)

Are dynamic data structures the only thing which is forbidden for
synthesis ?

No; there is a long list. Synthesis tools also differ; some things are
theoretically synthesisable but real tools don't handle them very well (e.g.
inferring 3x as much memory as required on ISE).

For a good example of how not to do it, look at the "Implementing sorting
algorithm" thread. Enno's comments are spot on.

Other non-synthable things:
real arithmetic, though there are efforts to remove this restriction.
file I/O (!)
processes with more than one clock signal (more generally, constructs which have
no viable hardware equivalent)
delays
output <= input after 50 ns;
If your hardware has a 100MHz clock signal, you can build a counter to count 5
cycles (50 ns) before driving output; or you can create a 5 stage pipeline
clocked at 100 MHz.

signal d1, d2, d3, d4 : std_logic;

Delay : process(clk) is
begin
if rising_edge(clk) then
d1 <= input;
d2 <= d1;
d3 <= d2;
d4 <= d3;
output <= d4;
end if;
end process;

or

Delay : process(clk) is
variable v1, v2, v3, v4, v5 : std_logic;
begin
if rising_edge(clk) then
output <= v5;
v5 := v4;
v4 := v3;
v3 := v2;
v2 := v1;
v1 := input;
end if;
end process;

Which illustrates some of the differences between signal and variable
assignments. Using variables in processes is neater, because the declarations
are local to the process. But because variables are updated immediately (as in
software) you have to describe your pipelines backwards! Incidentally, within a
process you can use procedures and functions, as in any other language, to
improve abstraction.

Signals are subject to "postponed assignment" between "delta cycles" (reading
hints which makes inter-process communication very clean and predictable,
and allows pipelines to be described in logical order. It also allows the
canonical "swap" to work!

Swap : process(clk) is
begin
if rising_edge(clk) then
A <= B;
B <= A;
end if;
end process;

Mike Treseler has some very good examples of coding style, for simulation and
synthesis; find and read them.

Peter Ashenden's book "A Designer's Guide to VHDL" is my recommendation.
(For a taster, his "VHDL Cookbook" is probably available online)

One word of warning: mixing signal assignment, within procedures, within a
process, is subject to synthesis bugs in XST, at least in ISE 7.1 and Webpack
9.2. I need to characterise this better sometime, and open a webcase.

I would be glad to have a running simulation and get some more
experience with the Xilinx ISE tool.
You can do a syntax check in Xilinx ISE. Is there also a check if the
code is ready for synthesis ?

Synthesise entities before they get too big. It'll either work or fail.

What is the better tool for simulation the Xilinx ISE simulator or the
Modelsim starter edition ?

Modelsim is pretty much the industry standard. I have never tried the ISE sim.

What is the difference between the free Xilinx ISE Webpack edition and
the comercial edition ?

If the Spartan-3/1500 isn't big enough, you need the full version...

- Brian