Newbie question about Wait for X and ModelSim

[GDan]

Hi,

I've got a XC9536-7 and have played with PE and MS. I've put a 1MHz
crystal on the global clock line in the veroboard mockup. In my tests
I've got some code as follows:

A <= '1';
wait for 10ns;
B <= '1';

Now I can see the above 10ns timing parameter in MS waveform view but
what I want to know is....

a). Is the "wait for x" statement only used in MS for simulation
purposes.

b). If the "wait for x" statement is used somehow within the device
while it's running; how does it know I've put a 1MHz crystal on the
clock line? I guess what I mean is how does the device keep internal
timing? and because I can put any time constant, does the system check
and make sure it's not totally out of range?

GD

 

[Jonathan Bromley]

On 16 Jun 2006 03:32:20 -0700, "GDan"
<coxsterdillon@hotmail.com> wrote:

Hi,

I've got a XC9536-7 and have played with PE and MS. I've put a 1MHz
crystal on the global clock line in the veroboard mockup. In my tests
I've got some code as follows:

A <= '1';
wait for 10ns;
B <= '1';

Now I can see the above 10ns timing parameter in MS waveform view

Indeed. The simulator processes the whole of the VHDL language,
and your wait statement is perfectly valid VHDL. It's just not
synthesisable to hardware.

a). Is the "wait for x" statement only used in MS for simulation
purposes.

It makes no sense for synthesis to hardware. I suspect that if
you trawl carefully through the XST compilation report you will
find a warning to the effect that the wait statement has been
ignored.

b). If the "wait for x" statement is used somehow within the device
while it's running; how does it know I've put a 1MHz crystal on the
clock line?

Good question. Of course, it doesn't. Synthesis simply cannot
build hardware to do what you asked for.

If you want to get one signal delayed relative to another, it may be
cleaner to do this sort of thing...

process (S)
begin
A <= S; -- copy S to A with zero delay
B <= S after 10 ns; -- B is delayed from S by 10 ns
end process;

Now you have a piece of code that's acceptable to all synthesis
tools and will simply copy S on to both A and B. However, by careful
tweaking of timing constraints within the Xilinx tools you may be able
to get a bigger delay on B than on A.

I would ask, though, why you want to do this. The time delay can
never be reliable - it's subject to process, temperature and
supply voltage variations - so you certainly can't use it,
for example, to build a 100MHz oscillator.

Mainstream modern design techniques are overwhelmingly
synchronous - you use an externally generated clock (exactly
as you are doing) to control all timing in the device. If you want
delays resolved to only 10ns then you'll need a 100MHz clock
(good luck to you, if you're doing it on stripboard!). With
a 1MHz clock you can easily get a 1us time delay simply
by putting a signal through a flip-flop clocked by the 1MHz.
Take a few hours to read any standard textbook on synchronous
design, or trawl back through the comp.lang.vhdl archives to
see some sensible examples, or even take a look at our
website. Ask here again when you've got
some specific issues to solve.

One hint: If you're using CPLDs on a stripboard prototype,
take a LOT of care to keep all the ground connections
as solid as possible - otherwise you risk getting strange
spurious behaviour because connections that are all
nominally 0-volts may flap around relative to each
other when the CPLD outputs make fast transitions.
Adding a resistor of about 50-100 ohms in series with
every output of the CPLD, RIGHT NEXT TO THE
OUTPUT PIN, is often very helpful on hacky prototypes
because it keeps the output currents fairly small.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[GDan]

Jonathan,

Thanks for your clear guidance. I understand and will search further
on VHDL that is not synthesisable.

I would ask, though, why you want to do this. The time delay can
never be reliable - it's subject to process, temperature and
supply voltage variations - so you certainly can't use it,
for example, to build a 100MHz oscillator.

Just to confirm the reason why I wanted to included a time delay. I
was modelling in VHDL a buffered sampled input bit to an output bit.
The input sample is taken on the rising edge of a clock signal and the
output is invoked by an output enable.

before:

CLK <= '1';
OE <= '0'; -- output enable

after:

CLK <= '1';
wait for 10ns;
OE <= '0'; -- output enable


When I had no delay statements in my test bench code, the waveform view
in MS procduced unexpected results (obvious when you consider it in
more detail) because the output enable was invoked at the sametime or
before the sample clock signal. I added the delay statements which are
fine if the signals are in the real world, i.e. on a pin which I
control and would adhere to the timing requirements. But my next
learning step was to move these signals from pins to internal signals
generated by a more complex design. I'd then got stumped on how i'd
make sure that the internal signals adhere to timing? Thats why I
posted.

Thanks,

GD



Jonathan Bromley wrote:

On 16 Jun 2006 03:32:20 -0700, "GDan"
coxsterdillon@hotmail.com> wrote:

Hi,

I've got a XC9536-7 and have played with PE and MS. I've put a 1MHz
crystal on the global clock line in the veroboard mockup. In my tests
I've got some code as follows:

A <= '1';
wait for 10ns;
B <= '1';

Now I can see the above 10ns timing parameter in MS waveform view

Indeed. The simulator processes the whole of the VHDL language,
and your wait statement is perfectly valid VHDL. It's just not
synthesisable to hardware.

a). Is the "wait for x" statement only used in MS for simulation
purposes.

It makes no sense for synthesis to hardware. I suspect that if
you trawl carefully through the XST compilation report you will
find a warning to the effect that the wait statement has been
ignored.

b). If the "wait for x" statement is used somehow within the device
while it's running; how does it know I've put a 1MHz crystal on the
clock line?

Good question. Of course, it doesn't. Synthesis simply cannot
build hardware to do what you asked for.

If you want to get one signal delayed relative to another, it may be
cleaner to do this sort of thing...

process (S)
begin
A <= S; -- copy S to A with zero delay
B <= S after 10 ns; -- B is delayed from S by 10 ns
end process;

Now you have a piece of code that's acceptable to all synthesis
tools and will simply copy S on to both A and B. However, by careful
tweaking of timing constraints within the Xilinx tools you may be able
to get a bigger delay on B than on A.

I would ask, though, why you want to do this. The time delay can
never be reliable - it's subject to process, temperature and
supply voltage variations - so you certainly can't use it,
for example, to build a 100MHz oscillator.

Mainstream modern design techniques are overwhelmingly
synchronous - you use an externally generated clock (exactly
as you are doing) to control all timing in the device. If you want
delays resolved to only 10ns then you'll need a 100MHz clock
(good luck to you, if you're doing it on stripboard!). With
a 1MHz clock you can easily get a 1us time delay simply
by putting a signal through a flip-flop clocked by the 1MHz.
Take a few hours to read any standard textbook on synchronous
design, or trawl back through the comp.lang.vhdl archives to
see some sensible examples, or even take a look at our
website. Ask here again when you've got
some specific issues to solve.

One hint: If you're using CPLDs on a stripboard prototype,
take a LOT of care to keep all the ground connections
as solid as possible - otherwise you risk getting strange
spurious behaviour because connections that are all
nominally 0-volts may flap around relative to each
other when the CPLD outputs make fast transitions.
Adding a resistor of about 50-100 ohms in series with
every output of the CPLD, RIGHT NEXT TO THE
OUTPUT PIN, is often very helpful on hacky prototypes
because it keeps the output currents fairly small.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Jonathan Bromley]

On 16 Jun 2006 04:21:51 -0700, "GDan"
<coxsterdillon@hotmail.com> wrote:

I added the delay statements which are
fine if the signals are in the real world, i.e. on a pin which I
control and would adhere to the timing requirements. But my next
learning step was to move these signals from pins to internal signals
generated by a more complex design. I'd then got stumped on how i'd
make sure that the internal signals adhere to timing? Thats why I
posted.

So, you have a race between two things happening: a data value
that is set up as the result of a clock edge, and an output enable
that someone somewhere will use to capture that data.
(Or perhaps I've misunderstood?) So you need the enable
to become asserted some time after the data has stabilised.

Generally you can't do this (in an FPGA or CPLD) by adding
asynchronous time delays. Even if you can persuade the tools
to build logic that has these time delays, you can't rely on their
values being consistent over temperature, process and supply
variations. So you need to control the delays synchronously:
set up the data on one clock cycle, assert the enable on the
next clock cycle. That means, of course, that you will
waste at least one clock cycle. This is partly why people
are moving to ever-faster clock frequencies. It also explains
why people are increasingly moving to synchronous
interfaces on memory and peripheral devices, so that you
can assert data and enable together and then push BOTH
into the device using a given clock edge.

From your posts I can't easily tell how much experience of
digital design you have - maybe you're already familiar with
the idea of a state machine, in which case you'll have no
difficulty in implementing the "one cycle delay" arrangement
I just described. If you're not familiar with FSMs, though,
I'm afraid you have quite a lot of work to plough through.

To help any further, we'd need more detail about what
external subsystem you're trying to interface with.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.