newbie question about logging internal quantities

[Nancy]

I am a newbie user of VHDL-AMS, and am trying to log quantities of a
module buried deep within the chip hierarchy at the chip testbench
level.

Here's the syntax I'm using in the entity, analog_ctrl_stim, to log
the quantity ain7_v inside of analog_ctrl_stim. It resides in the
hierarchy under :tb_ucxx:xtc_ucxx:xanalog_ctrl_stim.

entity analog_ctrl_stim is
port (
terminal AIN7 : electrical;
);
end analog_ctrl_stim;

architecture behav of analog_ctrl_stim is

quantity ain7_v across ain7_i through AIN7;

begin

test : process
begin

report "ain7 voltage = " & real'image(ain7_v); --- This works ok


end behav

Now, can I also log a quantity in a different part of the chip
hierarchy- for instance, :tb_ucxx:xucxx:xconv:xdac:v_dac1out. I have
been unable to find working syntax to log quantities in other parts of
the hierarchy at the analog_ctrl_stim level.

report "v_dac1out voltage = " &
real'imagetb_ucxx:xucxx:xconv:xdac:v_dac1out'reference); --- This
doesn't work

report "v_dac1out voltage = " &
real'image(":tb_ucxx:xucxx:xconv:xdac:v_dac1out"'reference); --- This
doesn't work either


Thanks for any help you all can provide. Perhaps this is just not
legal to do....but I have no clue.

 

[Sajan]

I think u should use a / instead of : .
try
report "v_dac1out voltage = " &
real'image(/tb_ucxx/xucxx/xconv/xdac/v_dac1out'reference);

I guess this should work.

Regs,
Sajan.

nancy.iida@ieee.org (Nancy) wrote in message news:<bf825f98.0402021349.35c78e1@posting.google.com>...

I am a newbie user of VHDL-AMS, and am trying to log quantities of a
module buried deep within the chip hierarchy at the chip testbench
level.

Here's the syntax I'm using in the entity, analog_ctrl_stim, to log
the quantity ain7_v inside of analog_ctrl_stim. It resides in the
hierarchy under :tb_ucxx:xtc_ucxx:xanalog_ctrl_stim.

entity analog_ctrl_stim is
port (
terminal AIN7 : electrical;
);
end analog_ctrl_stim;

architecture behav of analog_ctrl_stim is

quantity ain7_v across ain7_i through AIN7;

begin

test : process
begin

report "ain7 voltage = " & real'image(ain7_v); --- This works ok


end behav

Now, can I also log a quantity in a different part of the chip
hierarchy- for instance, :tb_ucxx:xucxx:xconv:xdac:v_dac1out. I have
been unable to find working syntax to log quantities in other parts of
the hierarchy at the analog_ctrl_stim level.

report "v_dac1out voltage = " &
real'imagetb_ucxx:xucxx:xconv:xdac:v_dac1out'reference); --- This
doesn't work

report "v_dac1out voltage = " &
real'image(":tb_ucxx:xucxx:xconv:xdac:v_dac1out"'reference); --- This
doesn't work either


Thanks for any help you all can provide. Perhaps this is just not
legal to do....but I have no clue.

 

[Nancy]

s_sajan_s@yahoo.com (Sajan) wrote in message news:<d244d444.0402022000.4d2338a9@posting.google.com>...

I think u should use a / instead of : .
try
report "v_dac1out voltage = " &
real'image(/tb_ucxx/xucxx/xconv/xdac/v_dac1out'reference);

Sajan-

Here's the error I got during vacom(VHDL-AMS compilation in Mentor
ADMS):

[Failure] Syntax error : received '/' while expecting '(' or '+' or
'-' or 'abs' or 'new' or 'not' or 'null' or 'open' or IDENTIFIER or
INTEGER LITERAL or FLOAT LITERAL or BASED LITERAL or CHAR LITERAL or
STRING LITERAL or BIT STRING LITERAL

If you have other ideas, let me know....not sure what to try at this
point.

Thanks,
Nancy

 

[Sajan]

Hi
I have a DAC model used in my testbench.
But its not in VHDL-AMS. The model is in VHDL alone.
But I guess the principles are the same.

The simulator is Modelsim.
As you have pointed out its not possible to probe internal signals.
So whenever there is a need to probe internal signals
we use signal_spy.

library modelsim_lib;
use modelsim_lib.util.all;
....

signal CDAC_OUTP_LOCAL : real;
begin
init_signal_spy("/top_firtb/Xanalog_top/Xcdac/CDAC_OUTP","CDAC_OUTP_LOCAL",1);

And then you could use something like:

process (CLK_DAC)
begin
if (CLK_DAC'event and CLK_DAC = '1') then
report "v_dac1out voltage = " & real'image(CDAC_OUTP_LOCAL);
end if;
end process;

Or else if you dont have the signal_spy functionality with your
simulator then probably you can try adding the report statement within
the DAC model itself so that you avoid the hierarchy. I guess there is
no other option.
Its better to refer the manual of your simulator to find out if any
similar utility as signal_spy exists.



nancy.iida@ieee.org (Nancy) wrote in message news:<bf825f98.0402030824.22497e2@posting.google.com>...

s_sajan_s@yahoo.com (Sajan) wrote in message news:<d244d444.0402022000.4d2338a9@posting.google.com>...
I think u should use a / instead of : .
try
report "v_dac1out voltage = " &
real'image(/tb_ucxx/xucxx/xconv/xdac/v_dac1out'reference);

Sajan-

Here's the error I got during vacom(VHDL-AMS compilation in Mentor
ADMS):

[Failure] Syntax error : received '/' while expecting '(' or '+' or
'-' or 'abs' or 'new' or 'not' or 'null' or 'open' or IDENTIFIER or
INTEGER LITERAL or FLOAT LITERAL or BASED LITERAL or CHAR LITERAL or
STRING LITERAL or BIT STRING LITERAL

If you have other ideas, let me know....not sure what to try at this
point.

Thanks,
Nancy

 

[Mike Treseler]

Nancy wrote:

Here's the error I got during vacom(VHDL-AMS compilation in Mentor
ADMS):

[Failure] Syntax error : received '/' while expecting '(' or '+' or
'-' or 'abs' or 'new' or 'not' or 'null' or 'open' or IDENTIFIER or
INTEGER LITERAL or FLOAT LITERAL or BASED LITERAL or CHAR LITERAL or
STRING LITERAL or BIT STRING LITERAL

Your vhdl testbench and your modelsim-tcl console
are different environments.

Read up on packages.
Your testbench cannot see anything out of the top scope.
Put the constants you want to print in a package and
compile the package into your work directory.

-- Mike Treseler