Newbie Question about Block Ram & Xilinx ECS

[Mole]

Hi All,

I am using ISE 6.1 Schematic entry, I have a RAMB4_S16_S16 symbol on my
sheet and I want to set the initial contents by setting the INIT_xx
Attributes in the object properties dialog box, when I simulate a Behavioral
model I get a whole bunch of errors like :

# ** Error: TopLevel.vhf(1480): No actual specified for ...
and ends with :
# ** Error: TopLevel.vhf(1482): near "port": expecting: END_

could someone please tell me what I am doing wrong .

also, what the heck is an "actual" :{

thanks.
Martin

 

[Phil Hays]

Mole wrote:

I am using ISE 6.1 Schematic entry, I have a RAMB4_S16_S16 symbol on my
sheet and I want to set the initial contents by setting the INIT_xx
Attributes in the object properties dialog box, when I simulate a Behavioral
model I get a whole bunch of errors like :

# ** Error: TopLevel.vhf(1480): No actual specified for ...
and ends with :
# ** Error: TopLevel.vhf(1482): near "port": expecting: END_

could someone please tell me what I am doing wrong .

also, what the heck is an "actual" :{

I don't use ISE schematic entry, but the error messages are familiar. It looks
very much like the schematic is being translated to VHDL for simulation. The
messages are the same I would get if I didn't have all connections to a lower level
block made. Is it possible that you don't have all pins of this RAMB4_S16_S16
connected?

If you understand VHDL at all, you might want to look at the TopLevel.vhf file
with a text editor and see what is going on.


--
Phil Hays

 

[Mole]

"Phil Hays" <SpamPostmaster@attbi.com> wrote in message
news:3FB64BA2.244E60DB@attbi.com...

I don't use ISE schematic entry, but the error messages are familiar. It
looks
very much like the schematic is being translated to VHDL for simulation.
The
messages are the same I would get if I didn't have all connections to a
lower level
block made. Is it possible that you don't have all pins of this
RAMB4_S16_S16
connected?

If you understand VHDL at all, you might want to look at the TopLevel.vhf
file
with a text editor and see what is going on.


--
Phil Hays

Hi Phil, thanks for the reply.

I dont need some of the connections, so you correctly speculated about the
connections, but I have tried making dummy connections but I still get the
same error messages I will have to get to grips with
HDL sooner than expected ...

Thanks, Martin