Newbie question about 500khz & 555

[Joe Plane]

I have an atmel 89C51 that needs to connect to an ADC808 which takes a
500Khz clock input & I would like the clock mechanism to be low noise,
what is the best mechanism?

Reading up on the 555 it says the R1 should be > 10k and the cap
should be greater that 1uF, however putting these into the equation
for the frequency I can't get close to 500khz.

Is the 7555 series a better choice and what combination of resistor &
capacitor would get this high?

Also is the best choice for low noise?

Thanks

 

[John Fields]

On 20 Oct 2003 16:21:57 -0700, jcpearce2005@yahoo.com (Joe Plane) wrote:

I have an atmel 89C51 that needs to connect to an ADC808 which takes a
500Khz clock input & I would like the clock mechanism to be low noise,
what is the best mechanism?

Reading up on the 555 it says the R1 should be > 10k and the cap
should be greater that 1uF, however putting these into the equation
for the frequency I can't get close to 500khz.

Is the 7555 series a better choice and what combination of resistor &
capacitor would get this high?
---

The 7555 is a better choice. Much lower quiescent current, no
high-current totem-pole glitch, less leakage current on the threshold
input, the list goes on and on...

There are a large number of RC combinations which will get you to 500kHz
and you can choose the one best for you by perusing the data sheet at:
---

http://pdfserv.maxim-ic.com/en/ds/ICM7555-ICM7556.pdf

Also is the best choice for low noise?

---
Depends on what you mean by noise. Phase noise? Jitter? What?

I don't think the 7555 is spec'ed for either, so you'll have to test it
or call them(?)if that's what what you're looking for.

--
John Fields

 

[John Fortier]

"Joe Plane" <jcpearce2005@yahoo.com> wrote in message
news:227cc17.0310201521.66f1c1ab@posting.google.com...

I have an atmel 89C51 that needs to connect to an ADC808 which takes a
500Khz clock input & I would like the clock mechanism to be low noise,
what is the best mechanism?

Reading up on the 555 it says the R1 should be > 10k and the cap
should be greater that 1uF, however putting these into the equation
for the frequency I can't get close to 500khz.

Is the 7555 series a better choice and what combination of resistor &
capacitor would get this high?

Also is the best choice for low noise?

Thanks

Joe,

The last time I ran into this problem, I used a spare CMOS gate and a 2 MHz
crystal to generate a digital signal and a 4013 dual D type flip flop as a
divide by four circuit. The flip flops removed any noise from the final
clock signal and it had exact mark/space equality at 500 KHz. If you are
using TTL levels, then the 74HC74 will perform the same function.

It's always easier to divide down than try to get a chip to operate right at
the edge of its normal frequency range. Even the 7555 has a top frequency
of only 500 KHz, so you would be using it at the edge of its capabilities.

If you like I can send you a circuit diagram. I don't use ASCII "circuit
diagrams" since they depend for clarity on the typeface used, and if mine is
different to yours I'd wind up sending something totally unintelligible.

Regards

John Fortier

 

[John Fields]

On Tue, 21 Oct 2003 01:42:45 GMT, "John Fortier"
<jfortier@rochester.rr.com> wrote:

"Joe Plane" <jcpearce2005@yahoo.com> wrote in message
news:227cc17.0310201521.66f1c1ab@posting.google.com...
I have an atmel 89C51 that needs to connect to an ADC808 which takes a
500Khz clock input & I would like the clock mechanism to be low noise,
what is the best mechanism?

Reading up on the 555 it says the R1 should be > 10k and the cap
should be greater that 1uF, however putting these into the equation
for the frequency I can't get close to 500khz.

Is the 7555 series a better choice and what combination of resistor &
capacitor would get this high?

Also is the best choice for low noise?

Thanks

Joe,

The last time I ran into this problem, I used a spare CMOS gate and a 2 MHz
crystal to generate a digital signal and a 4013 dual D type flip flop as a
divide by four circuit. The flip flops removed any noise from the final
clock signal and it had exact mark/space equality at 500 KHz. If you are
using TTL levels, then the 74HC74 will perform the same function.

It's always easier to divide down than try to get a chip to operate right at
the edge of its normal frequency range. Even the 7555 has a top frequency
of only 500 KHz, so you would be using it at the edge of its capabilities.

---
No, the 7555 has a _guaranteed_ fmax of 500kHz. In addition, it can be
configured as a 50% duty cycle astable by using the output to charge and
discharge the timing cap through the timinng resistor and ignoring the
DISCHARGE pin. Moreover, doing that gets rid of a crystal and its
supporting circuitry, the FF, and the spare CMOS gate. An entire chip if
no spare gate is available.
---

If you like I can send you a circuit diagram. I don't use ASCII "circuit
diagrams" since they depend for clarity on the typeface used, and if mine is
different to yours I'd wind up sending something totally unintelligible.

---
Use a non-proportional font like Courier and preface the drawing with
something like "View with XXXXXX", XXXXX being the font you used to
create the drawing.

--
John Fields

 

[Spehro Pefhany]

On 20 Oct 2003 16:21:57 -0700, the renowned jcpearce2005@yahoo.com
(Joe Plane) wrote:

I have an atmel 89C51 that needs to connect to an ADC808 which takes a
500Khz clock input & I would like the clock mechanism to be low noise,
what is the best mechanism?

Reading up on the 555 it says the R1 should be > 10k and the cap
should be greater that 1uF, however putting these into the equation
for the frequency I can't get close to 500khz.

Is the 7555 series a better choice and what combination of resistor &
capacitor would get this high?

The ADC808 will run at a wide range of clock frequencies. You could
consider driving a divider chain off the uP clock. If you are running
it at (say) 12MHz, you could use any 4-bit HCMOS counter to get a
750kHz clock. You drive it off the XTAL2 output with very short trace
length and reduce the load cap on that pin by 5pF or so (assuming you
are using the internal oscillator).

Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com

 

[Rich Grise]

Why do you need a whole nother oscillator? What do you have clocking
the 89C51? Just divide that down, or for that matter, assign an output
pin and bit-bang it.

Good Luck!
Rich

Joe Plane wrote:

I have an atmel 89C51 that needs to connect to an ADC808 which takes a
500Khz clock input & I would like the clock mechanism to be low noise,
what is the best mechanism?

Reading up on the 555 it says the R1 should be > 10k and the cap
should be greater that 1uF, however putting these into the equation
for the frequency I can't get close to 500khz.

Is the 7555 series a better choice and what combination of resistor &
capacitor would get this high?

Also is the best choice for low noise?

Thanks

 

[John Fortier]

"John Fields" <jfields@austininstruments.com> wrote in message
news:67a9pvsnru3ova741ta1qoodt52mf5sdof@4ax.com...

On Tue, 21 Oct 2003 01:42:45 GMT, "John Fortier"
jfortier@rochester.rr.com> wrote:


"Joe Plane" <jcpearce2005@yahoo.com> wrote in message
news:227cc17.0310201521.66f1c1ab@posting.google.com...
I have an atmel 89C51 that needs to connect to an ADC808 which takes a
500Khz clock input & I would like the clock mechanism to be low noise,
what is the best mechanism?

Reading up on the 555 it says the R1 should be > 10k and the cap
should be greater that 1uF, however putting these into the equation
for the frequency I can't get close to 500khz.

Is the 7555 series a better choice and what combination of resistor &
capacitor would get this high?

Also is the best choice for low noise?

Thanks

Joe,

The last time I ran into this problem, I used a spare CMOS gate and a 2
MHz
crystal to generate a digital signal and a 4013 dual D type flip flop as
a
divide by four circuit. The flip flops removed any noise from the final
clock signal and it had exact mark/space equality at 500 KHz. If you are
using TTL levels, then the 74HC74 will perform the same function.

It's always easier to divide down than try to get a chip to operate right
at
the edge of its normal frequency range. Even the 7555 has a top
frequency
of only 500 KHz, so you would be using it at the edge of its
capabilities.

---
No, the 7555 has a _guaranteed_ fmax of 500kHz. In addition, it can be
configured as a 50% duty cycle astable by using the output to charge and
discharge the timing cap through the timinng resistor and ignoring the
DISCHARGE pin. Moreover, doing that gets rid of a crystal and its
supporting circuitry, the FF, and the spare CMOS gate. An entire chip if
no spare gate is available.
---

If you like I can send you a circuit diagram. I don't use ASCII "circuit
diagrams" since they depend for clarity on the typeface used, and if mine
is
different to yours I'd wind up sending something totally unintelligible.

---
Use a non-proportional font like Courier and preface the drawing with
something like "View with XXXXXX", XXXXX being the font you used to
create the drawing.

--
John Fields

Actually, if you look at the other answers to this question, they advocate
using divide down circuitry. Whether you use a crystal oscillator or
available clock signals, the point is that its a simple exercise with
guaranteed results.

I used a crystal oscillator in my previous design because I needed several
other frequencies beside the 500 KHz and used aditional divider circuits to
achieve them. The advantage being that they were all frequency locked.
Using available clock signals to achieve the same purpose means that you too
will hace signals which are locked to each other, which may be an advantage.

By all means use the 7555 if it is best for your requirement, but
alternatives are available.

John Fortier

 

[Gerhard v d Berg]

"John Fortier" <jfortier@rochester.rr.com> wrote in message
news:ND8lb.40882$Sc7.29771@twister.nyroc.rr.com...

"John Fields" <jfields@austininstruments.com> wrote in message
news:67a9pvsnru3ova741ta1qoodt52mf5sdof@4ax.com...
On Tue, 21 Oct 2003 01:42:45 GMT, "John Fortier"
jfortier@rochester.rr.com> wrote:


"Joe Plane" <jcpearce2005@yahoo.com> wrote in message
news:227cc17.0310201521.66f1c1ab@posting.google.com...
I have an atmel 89C51 that needs to connect to an ADC808 which takes
a
500Khz clock input & I would like the clock mechanism to be low
noise,
what is the best mechanism?

Reading up on the 555 it says the R1 should be > 10k and the cap
should be greater that 1uF, however putting these into the equation
for the frequency I can't get close to 500khz.

Is the 7555 series a better choice and what combination of resistor &
capacitor would get this high?

Also is the best choice for low noise?

Thanks

Joe,

The last time I ran into this problem, I used a spare CMOS gate and a 2
MHz
crystal to generate a digital signal and a 4013 dual D type flip flop
as a
divide by four circuit. The flip flops removed any noise from the
final
clock signal and it had exact mark/space equality at 500 KHz. If you
are
using TTL levels, then the 74HC74 will perform the same function.

It's always easier to divide down than try to get a chip to operate
right at
the edge of its normal frequency range. Even the 7555 has a top
frequency
of only 500 KHz, so you would be using it at the edge of its
capabilities.

Snip ...

--
John Fields

Snip ....
By all means use the 7555 if it is best for your requirement, but
alternatives are available.

John Fortier


Hi Joe

I would not recommend a 555 oscillator to clock the ADC808 or other

noise sensitive circuits. The 555 or 7555 chips have high output drive

capability and tend to generate noise on the supply voltage due to the

shoot-through current of the 200ma output stage (pin3).



Flip-flops and counters also tends to be noisy - to many gates and

especially outputs, change states - this contributes to switching noise.

Running all devices from a single clock can prevent timing problems though.



I would recommend a 74HC14 (hex inverter) or 74HC132 (quad NAND)

CMOS Schmitt-trigger relaxation oscillator. These devices have (relatively)

low current outputs with reasonably well controlled output slew rates.



|\ 1/6 74HC14

_____| \o___

| | / |

| |/ |

| |

|___/\/\/\___|

| R

===

| C

|

--- 0V



T = 1/f = 0.6 RC to 0.8RC



(view with a fixed pitch font such as courier)

Remember to tie all spare CMOS inputs to Vcc (+5) or Ground (0 volt).



The CMOS circuit's frequency is not as stable with temperature and

supply variation as the 555, but is should be OK for the A-D clock.



For C < 50pf and R < 5K the circuit tends to be more temperature

and supply sensitive, as values approach input capacitance and output

resistance values. A low R will also results in a high power drain.

A to low R will also degrade output switching waveform - to much of a load.



For 500 KHz (2usec) I would recommend C = 100pf and R = 22K or 27k.

220pf and 10k - 15k should also work.



You could also use the 74HC132, remember to tie the other input high.

The free NAND input can be used to gate the oscillator on and off.



Gerhard van den Berg



(In e-mail address - reverse all characters after the @)

 

[Gerhard v d Berg]

"John Fortier" <jfortier@rochester.rr.com> wrote in message
news:ND8lb.40882$Sc7.29771@twister.nyroc.rr.com...

"John Fields" <jfields@austininstruments.com> wrote in message
news:67a9pvsnru3ova741ta1qoodt52mf5sdof@4ax.com...
On Tue, 21 Oct 2003 01:42:45 GMT, "John Fortier"
jfortier@rochester.rr.com> wrote:


"Joe Plane" <jcpearce2005@yahoo.com> wrote in message
news:227cc17.0310201521.66f1c1ab@posting.google.com...
I have an atmel 89C51 that needs to connect to an ADC808 which takes
a
500Khz clock input & I would like the clock mechanism to be low
noise,
what is the best mechanism?

Reading up on the 555 it says the R1 should be > 10k and the cap
should be greater that 1uF, however putting these into the equation
for the frequency I can't get close to 500khz.

Is the 7555 series a better choice and what combination of resistor &
capacitor would get this high?

Also is the best choice for low noise?

Thanks

Joe,

The last time I ran into this problem, I used a spare CMOS gate and a 2
MHz
crystal to generate a digital signal and a 4013 dual D type flip flop
as a
divide by four circuit. The flip flops removed any noise from the
final
clock signal and it had exact mark/space equality at 500 KHz. If you
are
using TTL levels, then the 74HC74 will perform the same function.

It's always easier to divide down than try to get a chip to operate
right at
the edge of its normal frequency range. Even the 7555 has a top
frequency
of only 500 KHz, so you would be using it at the edge of its
capabilities.

---
No, the 7555 has a _guaranteed_ fmax of 500kHz. In addition, it can be
configured as a 50% duty cycle astable by using the output to charge and
discharge the timing cap through the timinng resistor and ignoring the
DISCHARGE pin. Moreover, doing that gets rid of a crystal and its
supporting circuitry, the FF, and the spare CMOS gate. An entire chip if
no spare gate is available.

Snip ....

--
John Fields

Actually, if you look at the other answers to this question, they advocate
using divide down circuitry. Whether you use a crystal oscillator or
available clock signals, the point is that its a simple exercise with
guaranteed results.

I used a crystal oscillator in my previous design because I needed several
other frequencies beside the 500 KHz and used aditional divider circuits
to
achieve them. The advantage being that they were all frequency locked.
Using available clock signals to achieve the same purpose means that you
too
will hace signals which are locked to each other, which may be an
advantage.

By all means use the 7555 if it is best for your requirement, but
alternatives are available.

John Fortier

Hi Joe
I would not recommend a 555 oscillator to clock the ADC808 or other
noise sensitive circuits. The 555 or 7555 chips have high output drive

capability and tend to generate noise on the supply voltage due to the

shoot-through current of the 200ma output stage (pin3 ).



Flip-flops and counters also tends to be noisy - to many gates and

especially outputs, change state - this contributes to switching noise.



I would recommend a 74HC14 or 74HC132 CMOS Schmitt-trigger

relaxation oscillator. These devices have low current outputs

(relatively) with reasonably well controlled output slew rates.



|\ 1/6 74HC14

_____| \o___

| | / |

| |/ |

| |

|___/\/\/\___|

| R

===

| C

|

--- 0V



T = 1/f = 0.6 RC to 0.8RC



(view with a fixed pitch font such as courier)

Remember to tie all spare CMOS inputs to Vcc (+5) or Ground (0 volt).

If you use the 74HC132, tie the spare NAND input to +5v.

The spare NAND input can also be used to gate the oscillator.



The CMOS circuit's frequency is not as stable with temperature and

supply variation as the 555, but it should be OK for the A-D clock.



For C < 50pf and R < 5K the circuit tends to be more temperature

and supply sensitive, as values approach input capacitance and output

resistance values. It will also results in a high power drain.

A to small R will degrade output switching waveform - to much of a load.

(Max R is in the order of 10Meg and Max C is in the order of 10 - 50 uF)



For 500 KHz (2usec) I would recommend C = 100pf and R = 22K or 27k.

220pf and 10k - 15k should also work.



Gerhard van den Berg




(In e-mail address - reverse all characters in address after the @)

 

[John Woodgate]

I read in sci.electronics.design that Gerhard v d Berg
<gvdberg@az.oc.risc> wrote (in <3f9552f3$0$64719@hades.is.co.za&gt about
'Newbie question about 500khz & 555', on Tue, 21 Oct 2003:

The 555 or 7555 chips have high output drive

capability and tend to generate noise on the supply voltage due to the

shoot-through current of the 200ma output stage (pin3 ).

I thought that the 7555 didn't crowbar its supply.
--
Regards, John Woodgate, OOO - Own Opinions Only. http://www.jmwa.demon.co.uk
Interested in professional sound reinforcement and distribution? Then go to
http://www.isce.org.uk
PLEASE do NOT copy news posts to me by E-MAIL!

 

[John Fields]

On Tue, 21 Oct 2003 17:25:32 +0200, "Gerhard v d Berg"
<gvdberg@az.oc.risc> wrote:

Hi Joe
I would not recommend a 555 oscillator to clock the ADC808 or other

noise sensitive circuits. The 555 or 7555 chips have high output drive

capability and tend to generate noise on the supply voltage due to the

shoot-through current of the 200ma output stage (pin3).

---
The 555 does, but not the 7555
---

Flip-flops and counters also tends to be noisy - to many gates and

especially outputs, change states - this contributes to switching noise.

---
Synchronous counters (as opposed to ripple counters) obviate this
problem by having all Q outputs switch at the same time
---

--
John Fields

 

[Spehro Pefhany]

On Tue, 21 Oct 2003 17:25:32 +0200, the renowned "Gerhard v d Berg"
<gvdberg@az.oc.risc> wrote:

I would recommend a 74HC14 (hex inverter) or 74HC132 (quad NAND)
CMOS Schmitt-trigger relaxation oscillator. These devices have (relatively)
low current outputs with reasonably well controlled output slew rates.
snippage

Have you ever calculated the worst-case frequency tolerance using one
of these parts?

Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com

 

[Gerhard v d Berg]

"John Fields" <jfields@austininstruments.com> wrote in message
news:6inapv4ub8ao3q5387nh5j38ukh6gtf0s7@4ax.com...

On Tue, 21 Oct 2003 17:25:32 +0200, "Gerhard v d Berg"
gvdberg@az.oc.risc> wrote:

Hi Joe
I would not recommend a 555 oscillator to clock the ADC808 or other
noise sensitive circuits. The 555 or 7555 chips have high output drive
capability and tend to generate noise on the supply voltage due to the
shoot-through current of the 200ma output stage (pin3).
---
The 555 does, but not the 7555
---
Correct ! Mentioning the 7555 in the same breath as the 555 was a mistake.

-----

Flip-flops and counters also tends to be noisy - to many gates and
especially outputs, change states - this contributes to switching noise.
---
Synchronous counters (as opposed to ripple counters) obviate this
problem by having all Q outputs switch at the same time
--
John Fields
I had problems with synchronous counters - especially when many outputs

changed at the same time.
(counts changing from 0FFH to 00H and 07FH to 080H).
Counters with internal states and few outputs tend to generate less noise.
I had great success using a shift register (SR) as a 'counter'.
I shifted 1's in and detected when the leading '1' emerged at tap x.
Only one flip-flop changes state every clock as the 1's progress down the
SR.
The specific design could live with the noise when I cleared the SR.

4000 series CMOS devices are generally good for 'quiet' designs
(provided your design can live with the low speed of the 4000 series).

Gerhard van den Berg

 

[Gerhard v d Berg]

"Spehro Pefhany" <speffSNIP@interlogDOTyou.knowwhat> wrote in message
news:16qapvc9dln13039pjs4hrub1eunqvtqhm@4ax.com...

On Tue, 21 Oct 2003 17:25:32 +0200, the renowned "Gerhard v d Berg"
gvdberg@az.oc.risc> wrote:

I would recommend a 74HC14 (hex inverter) or 74HC132 (quad NAND)
CMOS Schmitt-trigger relaxation oscillator. These devices have
(relatively)
low current outputs with reasonably well controlled output slew rates.
snippage

Have you ever calculated the worst-case frequency tolerance using one
of these parts?

Best regards,
Spehro Pefhany

No I have not calculated worst-case tolerances, but have experienced
the problem.
Yes I agree, HC14 and HC132 Schmitt trigger oscilators should
not be used where one can't tolerate large frequency variations
(including initial, temperature and supply voltage variations).
In large production runs I would use such oscilators with care.

Gerhard van den Berg

 

[Bill Sloman]

"Gerhard v d Berg" <gvdberg@az.oc.risc> wrote in message
news:3f957d62$0$64726@hades.is.co.za...

<snip>

I had problems with synchronous counters - especially when many outputs
changed at the same time.
(counts changing from 0FFH to 00H and 07FH to 080H).
Counters with internal states and few outputs tend to generate less noise.
I had great success using a shift register (SR) as a 'counter'.
I shifted 1's in and detected when the leading '1' emerged at tap x.
Only one flip-flop changes state every clock as the 1's progress down the
SR.
The specific design could live with the noise when I cleared the SR.

A "Gray" code counter offers rather more states per bit - as many as binary
code counter - and only one transition per clock edge.

http://www.xilinx.co.jp/bvdocs/appnotes/xapp027.pdf

A Google search on " implementing Gray code counter" scored some 12,300
hits, including the above.

-------
Bill Sloman, Nijmegen

 

[Gerhard v d Berg]

"Bill Sloman" <bill.sloman@ieee.org> wrote in message
news:bn4dm2$19o$1@reader11.wxs.nl...

"Gerhard v d Berg" <gvdberg@az.oc.risc> wrote in message
news:3f957d62$0$64726@hades.is.co.za...

snip

I had problems with synchronous counters - especially when many outputs
changed at the same time.
(counts changing from 0FFH to 00H and 07FH to 080H).
Counters with internal states and few outputs tend to generate less
noise.
I had great success using a shift register (SR) as a 'counter'.
I shifted 1's in and detected when the leading '1' emerged at tap x.
Only one flip-flop changes state every clock as the 1's progress down
the
SR.
The specific design could live with the noise when I cleared the SR.

A "Gray" code counter offers rather more states per bit - as many as
binary
code counter - and only one transition per clock edge.

http://www.xilinx.co.jp/bvdocs/appnotes/xapp027.pdf

A Google search on " implementing Gray code counter" scored some 12,300
hits, including the above.

I once used a "Grey"code counter in a decoder where I had to eliminate a
glitch in the decoding logic.
Documenting "Grey" code counters designs required a lot of extra work
as this "funny" counter confused most readers.
(The "Why complicate the design?" question was difficult to counter)

I also tried a "Grey" code counters using 20V8 & 22V10 GALs
where I needed low noise, but normal GALs and PALs are not the
quietest logic devices available.
I could not found any native "Grey" code counter ICs. Most designs and
implementations seem to employ normal binary counters with XORs
on the outputs which, aren't glitch free and defeats the purpose.

Gerhard van den Berg

 

[John Woodgate]

I read in sci.electronics.design that Gerhard v d Berg
<gvdberg@az.oc.risc> wrote (in <3f964101$0$64721@hades.is.co.za&gt about
'Newbie question about 500khz & 555', on Wed, 22 Oct 2003:

I once used a "Grey"code counter in a decoder

The adjective is spelt 'gray' in US English but 'grey' in British
English. The code person is always 'Gray'.
--
Regards, John Woodgate, OOO - Own Opinions Only. http://www.jmwa.demon.co.uk
Interested in professional sound reinforcement and distribution? Then go to
http://www.isce.org.uk
PLEASE do NOT copy news posts to me by E-MAIL!

 

[John Fields]

On Wed, 22 Oct 2003 17:34:38 +0100, John Woodgate
<jmw@jmwa.demon.contraspam.yuk> wrote:

The adjective is spelt 'gray' in US English but 'grey' in British
English. The code person is always 'Gray'.

---
'Spelt' is spelt 'spelled' in US English, but you knew that!^)

--
John Fields

 

[Ben Bradley]

In sci.electronics.design, jcpearce2005@yahoo.com (Joe Plane) wrote:

I have an atmel 89C51 that needs to connect to an ADC808 which takes a
500Khz clock input & I would like the clock mechanism to be low noise,
what is the best mechanism?

Reading up on the 555 it says the R1 should be > 10k and the cap
should be greater that 1uF, however putting these into the equation
for the frequency I can't get close to 500khz.

Is the 7555 series a better choice and what combination of resistor &
capacitor would get this high?

Also is the best choice for low noise?

The best would be a well-bypassed (which you should always do
anyway) ripple counter/divider from the processor's crystal
oscillator. Any R-C based oscillator is sure to have more jitter than
a crystal-derived clock, and that will be seen as noise in the
digitized samples.
OTOH, an ADC808 is (IIRC, and it's been a while) only an 8-bit
device, so clock-jitter vs. power rail noise isn't going to make much
difference. I'd have to know more about the application, but so far my
temptation would be to do what's cheapest.

Thanks

I hope I didn't use too many arcane FLA's...

 

[Joe Plane]

The ADC808 will run at a wide range of clock frequencies. You could
consider driving a divider chain off the uP clock. If you are running
it at (say) 12MHz, you could use any 4-bit HCMOS counter to get a
750kHz clock. You drive it off the XTAL2 output with very short trace
length and reduce the load cap on that pin by 5pF or so (assuming you
are using the internal oscillator).

Best regards,
Spehro Pefhany

Uhh, a little too fast for my proverbial walking legs.

A 'divider chain?' Is there a place I can read up on this?

And when you say using a 4 bit HCMOS counter do you mean using one of
the internal uP counters and then oscillating one of it's IO pins at a
cycle to generate 750Khz?

More generally is it a typical practice to use a uP pin as a clock for
another device and 'manually' set and unset this pin in the software?

Many thanks for all the replies.