Newbie Q: State Machine Book Recommendations

  • Thread starter Jeffrey W. Travis
  • Start date
J

Jeffrey W. Travis

Guest
Greetings --

I am looking for recommendations for a good book on state machine design
theory and practice, particularly in VHDL. I found one book online,
"Digital Logic and State Machine Design," by David Comer. Is it any
good? What other books have you had good experience with?

I am sort of an old-school generalist (analog/digital) who is trying to
update his skill mix. In 2 previous VHDL design projects (small CPLD's)
I was able to get by using entity/architecture pairs that reproduced the
function of the 74LSxx parts us old guys know and love, then using
component instantiation in higher-level entities to "wire" them together
into functional blocks. However, in my current project I sense that
this approach will not be suitable.

Any recommendations would be greatly appreciated.

Jeff Travis
 
Jeffrey W. Travis wrote:

Greetings --

I am looking for recommendations for a good book on state machine design
theory and practice, particularly in VHDL. I found one book online,
"Digital Logic and State Machine Design," by David Comer. Is it any
good? What other books have you had good experience with?

I am sort of an old-school generalist (analog/digital) who is trying to
update his skill mix. In 2 previous VHDL design projects (small CPLD's)
I was able to get by using entity/architecture pairs that reproduced the
function of the 74LSxx parts us old guys know and love, then using
component instantiation in higher-level entities to "wire" them together
into functional blocks. However, in my current project I sense that
this approach will not be suitable.

Any recommendations would be greatly appreciated.

Jeff Travis
Click to expand...
1. Stephen D. Brown and Zvonko G. Vranesic, Try Fundamentals of Digital
Logic with VHDL Design, McGraw-Hill, 2000.

It includes state-machine design with VHDL, although it's also
targeted at those who are just learning digital design. There is a
very good appendix with concise examples of various VHDL statements
along with a list of common errors in VHDL.

2. James O. Hamblen and Michael D. Furman, Rapid Prototyping of Digital
Systems, 2nd edition, Kluwer Academic Publishers, 2001.

This book uses a tutorial approach. It includes an implementation
of a MIPS computer---albeit, somewhat pared down---which is a good
example of how to implement a quite elaborate state machine.

3. Douglas L. Perry, VHDL Programming by Example, 4th edition,
McGraw-Hill, 2002.

I haven't yet read this book so I don't know how useful you might
find it but it's on a list of recommended books so I got a copy
recently.

4. J. Bhasker, A VHDL Synthesis Primer, 2nd edition, Star Galaxy
Publishing, Allentown, PA, 1998.

This book explains the way VHDL code gets synthesized and contrasts
that with the way simulators interpret the code. The fact that
there exists a mismatch is an inconvenient fact and knowing how to
write your code to avoid mismatches is useful.

5. John W. Carter, Digital Designing with Programmable Logic Devices,
Prentice Hall,1997.

While it doesn't treat VHDL at all, it does use CUPL as an example
of an HDL. Mostly the book uses graphical techniques. What I
especially like about this book, though, is its excellent treatment
of the design of state machines from scratch and how to implement
them in PLDs, ROMS, and discrete gates generally. It has an
excellent section on how to eliminate glitches by the use of
delayed-state timing. It also includes the development of a CPU
very similar to the Motorola 6500, using a microcoded design.

I hope this proves helpful to you.

Charles B. Cameron
 
I don't know who would dedicate a book to this. I personally avoid using
them as they create oogles of logic as they grow (which they will) and hence
timing/fitting problems. State machine examples in books are illustrated
with a data type definition (for clarity) and the case statement. Be aware
of the trade-offs to this approach. They can also be implemented (in effect)
using any combinatorial statements. .
 
In article <O2o1c.55408$n77.12697@newssvr33.news.prodigy.com>,
nospam@nospam.com says...
I don't know who would dedicate a book to this. I personally avoid using
them as they create oogles of logic as they grow (which they will) and hence
timing/fitting problems. State machine examples in books are illustrated
with a data type definition (for clarity) and the case statement. Be aware
of the trade-offs to this approach. They can also be implemented (in effect)
using any combinatorial statements. .

Hmmm . . . interesting viewpoint. Are you saying here that my old-
Click to expand...
school method of wiring together TTL-style entities works as well or
better?

Jeff Travis
 
[This followup was posted to comp.lang.vhdl and a copy was sent to the
cited author.]

In article <40460506.4000409@aplcenmp.apl.jhu.edu>,
cameronc@aplcenmp.apl.jhu.edu says...
Jeffrey W. Travis wrote:

Greetings --

I am looking for recommendations for a good book on state machine design
theory and practice, particularly in VHDL. I found one book online,
"Digital Logic and State Machine Design," by David Comer. Is it any
good? What other books have you had good experience with?

I am sort of an old-school generalist (analog/digital) who is trying to
update his skill mix. In 2 previous VHDL design projects (small CPLD's)
I was able to get by using entity/architecture pairs that reproduced the
function of the 74LSxx parts us old guys know and love, then using
component instantiation in higher-level entities to "wire" them together
into functional blocks. However, in my current project I sense that
this approach will not be suitable.

Any recommendations would be greatly appreciated.

Jeff Travis


1. Stephen D. Brown and Zvonko G. Vranesic, Try Fundamentals of Digital
Logic with VHDL Design, McGraw-Hill, 2000.

It includes state-machine design with VHDL, although it's also
targeted at those who are just learning digital design. There is a
very good appendix with concise examples of various VHDL statements
along with a list of common errors in VHDL.

2. James O. Hamblen and Michael D. Furman, Rapid Prototyping of Digital
Systems, 2nd edition, Kluwer Academic Publishers, 2001.

This book uses a tutorial approach. It includes an implementation
of a MIPS computer---albeit, somewhat pared down---which is a good
example of how to implement a quite elaborate state machine.

3. Douglas L. Perry, VHDL Programming by Example, 4th edition,
McGraw-Hill, 2002.

I haven't yet read this book so I don't know how useful you might
find it but it's on a list of recommended books so I got a copy
recently.

4. J. Bhasker, A VHDL Synthesis Primer, 2nd edition, Star Galaxy
Publishing, Allentown, PA, 1998.

This book explains the way VHDL code gets synthesized and contrasts
that with the way simulators interpret the code. The fact that
there exists a mismatch is an inconvenient fact and knowing how to
write your code to avoid mismatches is useful.

5. John W. Carter, Digital Designing with Programmable Logic Devices,
Prentice Hall,1997.

While it doesn't treat VHDL at all, it does use CUPL as an example
of an HDL. Mostly the book uses graphical techniques. What I
especially like about this book, though, is its excellent treatment
of the design of state machines from scratch and how to implement
them in PLDs, ROMS, and discrete gates generally. It has an
excellent section on how to eliminate glitches by the use of
delayed-state timing. It also includes the development of a CPU
very similar to the Motorola 6500, using a microcoded design.

I hope this proves helpful to you.

Charles B. Cameron


Thanks for the tips, Charles! I will look into these texts.
Click to expand...

Jeff Travis
 
Hmmm . . . interesting viewpoint. Are you saying here that my old-
school method of wiring together TTL-style entities works as well or
better?
Click to expand...
You have to think about it with respect to the target technology and the
resources availible in your design.

Strict structural VHDL is pointless since all you really end up with is a
schematic netlist. You do get good control of the design that way but little
benefit of the language and it's readability.

Case statements are synthesized as a unit and can grow (or be) in to large
objects. This means they are less flexible for routing/fitting and can
create timing problems.
 
Jeffrey W. Travis wrote:

In 2 previous VHDL design projects (small CPLD's)
I was able to get by using entity/architecture pairs that reproduced the
function of the 74LSxx parts us old guys know and love, then using
component instantiation in higher-level entities to "wire" them together
into functional blocks. However, in my current project I sense that
this approach will not be suitable.

Any recommendations would be greatly appreciated.
Click to expand...
A state machine is a quite limited subset of the
synthesizable descriptions available in the
synchronous vhdl process template. If you
want to try a vhdl description, focus first on learning
the synchronous process.

related thread:
http://groups.google.com/groups?q=state_example

-- Mike Treseler
 
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