newbie: pipeline adder module instantiation problem

[Makhan]

hello all,

I am new to verilog and I have a simple problem regarding pipeline 8
bit adder. The 1 bit adder is simply as:
assign {carry, sum} = a + b + cin;
which simulates fine. Similarly there is a one bit register for
storing the intermediate carry result as:
=================
reg q;
always@(posedge clk or negedge rstn)
if(rstn == 1'b0) q <= 1'b0;
else q <= d;
=================
however, when I instantiate these modules and interface them in the 8
bit pipeline, I notice from simulation results that

input of 1 bit carry register is high Z and the output is X all the
time, becuase of which, the adder does not perform the

addition correctly. The code is as follows:
=====================
module adder8(clk, rstn, a, b, SUM);

input clk;
input [7:0] a;
input [7:0] b;
input rstn;
output [7:0] SUM;

//defining wires for input and output interfacing
reg A, B;
reg [7:0] sum_reg;
wire sum_in;
integer i=0;

always@(posedge clk) begin
if (i < 9 && rstn == 1'b1) begin
A = a;
B = b;
sum_reg <= sum_in;
//SUM <= sum_in;
i = i +1;
end
end

adder1 U0(
.a(A), .b(B), .cin(1'b0),
.carry(d), .sum(sum_in));
register Sum( // 8 bit register for storing outputs of 1bit adder
.clk(clk), .rstn(rstn),
.qreg(SUM), .dreg(sum_reg)); // -> SUM, <- sum of one bit
reg1 carry_reg(
.clk(clk), .rstn(rstn),
.q(cin), .d(carry)); // i <- carry of 1bit adder

endmodule
=====================
Is it illegal to interface the output of one instantiated module into
the input of another instantiated module within top

module? In the case here, the output of carry out of 1 bit
adder(carry) into 1 bit register(d), and output of 1 bit

register(q) to cin?

Furthermore, are there any free synthesis tools which could help me
see the synthesized logic of my written Verilog code?


Thanks in advance,

Makhan

 

[Jim Wu]

=====================
module adder8(clk, rstn, a, b, SUM);

input clk;
input [7:0] a;
input [7:0] b;
input rstn;
output [7:0] SUM;

//defining wires for input and output interfacing
reg A, B;
reg [7:0] sum_reg;
wire sum_in;
integer i=0;

always@(posedge clk) begin
if (i < 9 && rstn == 1'b1) begin
A = a;
B = b;
sum_reg <= sum_in;
//SUM <= sum_in;
i = i +1;
end
end

adder1 U0(
.a(A), .b(B), .cin(1'b0),
.carry(d), .sum(sum_in));
register Sum( // 8 bit register for storing outputs of 1bit adder
.clk(clk), .rstn(rstn),
.qreg(SUM), .dreg(sum_reg)); // -> SUM, <- sum of one bit

reg1 carry_reg(
.clk(clk), .rstn(rstn),
.q(cin), .d(carry)); // i <- carry of 1bit adder
^^^^

"carry" signal has no driver.

Jim Wu
jimwu88NOOOSPAM@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips