[Newbie] Output pins are stuck at VCC or GND

[Tomek Zieliński]

Helo!

This is ma first code in Verilog. It is simple clock.

module zegar(clk);
output clk;
reg clk;
parameter period=500;
always begin
#(period/2) clk=1;
#(period/2) clk=0;
end
endmodule

There is a warning during compilation (Quartus 4.2): Warning: Pin "clk"
stuck at GND.
What is wrong?

Best Regards
Thomas Zielinski

 

[info_]

Tomek Zieliński wrote:

Helo!

This is ma first code in Verilog. It is simple clock.

module zegar(clk);
output clk;
reg clk;
parameter period=500;
always begin
#(period/2) clk=1;
#(period/2) clk=0;
end
endmodule

There is a warning during compilation (Quartus 4.2): Warning: Pin "clk"
stuck at GND.
What is wrong?

Best Regards
Thomas Zielinski

Are you describing actual silicon ?

This code is for simulation : it is a stimulus.

You are trying to synthesize this behaviour into gates (LUts)
and Flip Flops : no way.

An FPGA usually has a clock _input_.

I suggest you read some literature about FPGAs, synthesis, HDLs
etc... before running the tools, otherwise you will run into
a lot of trouble and have none of the great fun FPGA Design
may provide.
My opinion indeed.

Bert Cuzeau

 

[Mike Lewis]

"Tomek Zieliński" <thomas_zNOSPAM@poczta.onet.pl> wrote in message
news:d5j6an$4tl$1@nemesis.news.tpi.pl...

Helo!

This is ma first code in Verilog. It is simple clock.

module zegar(clk);
output clk;
reg clk;
parameter period=500;
always begin
#(period/2) clk=1;
#(period/2) clk=0;
end
endmodule

There is a warning during compilation (Quartus 4.2): Warning: Pin "clk"
stuck at GND.
What is wrong?

Best Regards
Thomas Zielinski

try removing the clk=0 and changing the clk=1 to clk=!clk.

And as the other poster mentioned this is only particular to
the simulation environemnt and cannot be synthesized.