newbie: integer to bit_vector

[Schüle Daniel]

Hello,

I want to write a simple test benchmark
I want to generate all possible bit combinations
for bit_vector(7 downto 0) through an integer variable

eg

for i in 0 to 255 loop
bv <= convert(8, i); -- 8 width, and i value
end loop;

is there some convert function for this purpose?

I couldn't find it using google
too much information but not what I am looking for

Regards, Daniel

 

[KJ]

Assuming 'bv' is std_logic_vector(7 downto 0)...

And you include the IEEE numeric_std library...
library IEEE;
use IEEE.numeric_std.all;

then....
for i in 0 to 255 loop
bv <= std_logic_vector(to_unsigned(i, bv'length)); -- 8 width, and i
value
end loop;

KJ

 

[KJ]

Oops...just noticed that you wanted 'bv' to be a bit_vector....well, you can
work out that last conversion I'm sure.
KJ

"KJ" <kkjennings@sbcglobal.net> wrote in message
news:OaKeg.35999$4L1.5603@newssvr11.news.prodigy.com...

Assuming 'bv' is std_logic_vector(7 downto 0)...

And you include the IEEE numeric_std library...
library IEEE;
use IEEE.numeric_std.all;

then....
for i in 0 to 255 loop
bv <= std_logic_vector(to_unsigned(i, bv'length)); -- 8 width, and i
value
end loop;

KJ

 

[KJ]

First nclude the IEEE numeric_std library...
library IEEE;
use IEEE.numeric_std.all;

then....

for i in 0 to 255 loop
bv <= bit_vector(to_unsigned(i, bv'length)); -- 8 width, and i value
end loop;

KJ

 

[Andy]

Use numeric_bit instead of numeric_std package.

It defines signed and unsigned vectors of bit instead of std_logic.

So type conversions from numeric_bit.unsigned to bit are allowed:

bit_vector(unsigned(int_val)) works as long as numeric_bit is used.

Andy
KJ wrote:

First nclude the IEEE numeric_std library...
library IEEE;
use IEEE.numeric_std.all;

then....

for i in 0 to 255 loop
bv <= bit_vector(to_unsigned(i, bv'length)); -- 8 width, and i value
end loop;

KJ

 

[Schüle Daniel]

thx, it works fine