newbie: help with synchronisation

[Justas P]

Hello there,

I am new to verilog and just starting with some examples. Now I am
trying to interface microcontroller to cpld chip. uC runs faster than
cpld chip and I am using 8 bits wide parallel data connection. CPLD
chip reads data on cpld inputs on rising clock edge. The problem for
me is how to know that CPLD got the data I made available on uC
outputs - just add an delay that is as long as one clock cycle of cpld
or are there other ways of ensuring that?

Thanks,
Justin

 

[perich]

Hello Justas,

Whenever you want to transfer data from one clock-domain to another,
you should always make sure that the block (clock-domain) offering the
data is somehow at the same or a lower frequency than the block (clock-
domain) receiving the data. In that case the data to be transferred
can be sampled at least once (or multiple times).

The best solution would be if both your blocks (uC+CPLD) could be
clocked at the same frequency (or if at least the part of your CPLD
that reads the data could be clocked by the uC clock), but I am not
sure if a CPLD accepts an external clock (maybe somebody else on this
forum can shed some light on this or has some experience with this?).

Otherwise the easiest solution would probably be to have the uC output
the same data during a couple of consecutive (uC) clock cycles. Long
enough for the CPLD to be able to sample the data at least once.

I hope this is somehow helpful.

Cheers,
Patrick

 

[Mike Treseler]

Justas P wrote:

The problem for
me is how to know that CPLD got the data I made available on uC
outputs - just add an delay that is as long as one clock cycle of cpld
or are there other ways of ensuring that?

Using a handshake.
A cpld state machine might synchronize
and watch the chip select and write enable from the cpu
before sampling the data and sending an ack back to the cpu.
http://inst.eecs.berkeley.edu/~cs150/sp02/lectures/lec28-asynch-6up.pdf

-- Mike Treseler

 

[Justas P]

On Nov 23, 11:45 pm, Mike Treseler <mtrese...@gmail.com> wrote:

Justas P wrote:
The problem for
me is how to know that CPLD got the data I made available on uC
outputs - just add an delay that is as long as one clock cycle of cpld
or are there other ways of ensuring that?

Using a handshake.
A cpld state machine might synchronize
and watch the chip select and write enable from the cpu
before sampling the data and sending an ack back to the cpu.http://inst.eecs.berkeley.edu/~cs150/sp02/lectures/lec28-asynch-6up.pdf

     -- Mike Treseler

Thanks for a link! Is there a book you might recommend about
asynchronous communication? I would like to get a little bit more
information about this.

 

[Mike Treseler]

Justas P wrote:

Thanks for a link! Is there a book you might recommend about
asynchronous communication?

Your best specific information will come from
the data sheets and ap notes for your
cpu and interface chips, and from trial and error.

I like the mit and berkeley lecture notes for
up-to-date practices. The subject gets
mininal coverage in textbooks, but search
amazon. There might be something new.

-- Mike Treseler