Newbie Help: How do I deal with variable length vectors?

I have an entity that has two std_logic_vectors as inputs (see below).
I want to make it so when I instantiate a component of this entity, it
will arrange itself in response to the width of the vectors it receives
as an inputs.

The architecture below shows that I try to take the width of the input
vector (shared variable Width: integer:= A'length and then create
signals with that width. These signals then link together some
subcomponents (which attempt to do the same thing to discover the
vector width).

The obvious problem is that the input vectors are not initialized when
this code runs, so A'length returns 0, and the linking vectors created
are useless. I cannot use a "wait on" statement to wait until the input
vectors are initialized, becuase this is a concurrent statement block.

It seems like I'm trying to do a combination of sequential and
concurrent statements, which is not proper VHDL. How can I get around
this problem? I'm still quite new to VHDL, so any information you can
give me would be greatly appreciated.

Thanks!

The entity:

entity SquareRoot is
port(
A, B: in std_logic_vector;
Cin: in std_logic;
Cout: out std_logic;
Sum: out std_logic_vector
);
end;

The architecture:

architecture behav of SquareRoot is
--removed component declarations

shared variable Width: integer:= A'length;
signal Plink, Glink, Slink0, Slink1: std_logic_vector(width-1 downto
0);
signal Clink0, Clink1: std_logic;

begin
pg: pAndG port map (A, B, Plink, Glink);
a0: sradderc0 port map (Plink, Glink, Clink0, Slink0);
a1: sradderc1 port map (Plink, Glink, Clink1, Slink1);
mx: mux port map (Cin, Slink0, Slink1 , Clink0, Clink1, Sum, Cout);
end;

 

Thank you Ulf. I was not aware of generics, but they appear to be
exactly what I needed.

Thanks agains for your help.

 

Hi Bert,

Thank you for the advice. To be honest, I only had shared variables
becuase a compilation error suggested it

I do not need to simulate this particular code, but in the future I
will take your advice and try it out on the Xilinx synthesizer I am to
use.

Thank again for your help.