Newbie CAN Core question - Student

[Fouad]

Hi,
I'm new to FPGA's... I have a problem that requires me to use a VHDL CAN
(Controller area Network) Core... I got the core from an open source..
and I get an error as below:

FATAL_ERROR:Xstortability/export/Port_Main.h:126:1.13 - This
application has discovered an exceptional condition from which it
cannot recover. Process will terminate. To resolve this error,
please consult the Answers Database and other online resources at
http://support.xilinx.com. If you need further assistance, please open
a Webcase by clicking on the "WebCase" link at
http://support.xilinx.com
Error: XST failed

the support page doesn't give me any help as they haven't covered this
error yet...
any ideas?

can anyone suggest another freely available CAN core?

Thanks for all your help in advance.

Fouad

 

[Antti Lukats]

f.sethna@sussex.ac.uk (Fouad) wrote in message news:<8c409408.0309030218.7d94baef@posting.google.com>...

Hi,
I'm new to FPGA's... I have a problem that requires me to use a VHDL CAN
(Controller area Network) Core... I got the core from an open source..
and I get an error as below:

FATAL_ERROR:Xstortability/export/Port_Main.h:126:1.13 - This
the support page doesn't give me any help as they haven't covered this
error yet... any ideas?

this happens pretty often its similar to Windows GPF fault - if something
is internally wrong with XST it fails with that Port_main.h:126 ...

hope it will be better with the next release of ISE so far no cure is known.

TRY - clean project, close ISE start over try again, sometimes the problem
goes away by itself, if that doesnt help try to

UUPS this time it DOES NOT HELP

both vhdl and verilog version fail
I guess the problem is in bad verilog/vhdl support for array types
so the problem could be solved by rewriting the
can_fifo.v or can_fifo.vhd

note that the fatal error occours on can_bsp module not can_fifo module

try: replace can_fifo with known-good-dummy module try to synthesize
if success then seek find and correct the XST problem, and PLEASE
let as know if you succeed to find and/or correct the problem!

can anyone suggest another freely available CAN core?

try both VHLD and Verilog versions, maybe one of them goes OK
see above, not this time

all other(s) are commercial $$$