new2verilog

[uzma]

Hi

i m a begginer in verilog. I have a project that i have to develop a
square wave that can vary its pulse width and frequency can any body help
???????

regards

 

[uzma]

Hi Mark

thanx alot but the problem i m facing now is that there is an error in the
simultion ie

near "else" expecting IDENT

i m unable to comprehend it will u plz help in this regard

Regards
Uzma

 

[glen herrmannsfeldt]

uzma wrote:

Hi Mark

thanx alot but the problem i m facing now is that there is an error in the
simultion ie

near "else" expecting IDENT

i m unable to comprehend it will u plz help in this regard

I think that means a ; is in the wrong place.

A good guess, anyway. I don't have problems with it quite
as often as I should, but end doesn't have a ; after it.
(Compared to PL/I where it does.)

-- glen

 

[Swapnajit Mittra]

"uzma" <uzma_uet@yahoo.com> wrote in message news:<f188105389be2296005f51f5cb7a3a62@localhost.talkaboutprogramming.com>...

Hi

i m a begginer in verilog. I have a project that i have to develop a
square wave that can vary its pulse width and frequency can any body help
???????

regards

Since you are new to Verilog and presumably new to
this newsgroup too, here is a mandatory word of
caution: do not try to get your homework done by
others through this group or otherwise

Having said that, here are some hints:

First, find out how to generate a clock in Verilog.
Few important things to observe are: (1) A clock
*always* toggles. (2) It *initiates* from a known
value (either 0 or 1). (3) Then for the duration
of the high state, it stays at 1 followed by the
duration of the low state, when it stays at 0. (4) The
duration of the high or the low states can be either
hard coded (5, 15 etc.) or can be *parameterized*.
It can even be dependent on *input* values.

Now, grab a Verilog text and you are ready to go.
And while you are at it: is the code that you have
just written *synthesizable*?

- Swapnajit.
--
SystemVerilog DPI tutorial on Project VeriPage:
http://www.project-veripage.com/dpi_tutorial_1.php
For subscribing to Project VeriPage mailing list:
<URL: http://www.project-veripage.com/list/?p=subscribe&id=1>

 

[weizbox]

"uzma" <uzma_uet@yahoo.com> wrote in message news:<f188105389be2296005f51f5cb7a3a62@localhost.talkaboutprogramming.com>...

Hi

i m a begginer in verilog. I have a project that i have to develop a
square wave that can vary its pulse width and frequency can any body help
???????

regards

If you have Xilinx ISE, it has an example of PWM that might help you
get started. Its in the language templates under Verilog->Synthesis
Contructs->Common Functions->Misc->Pulse Width Modulation Circuit.

Not sure if this will help you fulley, but it might be a good
reference. Like suggested by Swapnajit, I would start with getting a
basic clock running, thats the base of which everyhting else will fall
into.

Heres a Basic counter in Verilog that I made. Keep in mind tho, that I
am a n00b as well and only started getting into Verilog a few weeks
ago, so if anyone else has somthing to add, please do.


module (clk, led);

input clk; // <=== Connect this to the clock pin on your board.
output reg led; // <=== LED output and reg(not needed but good as a
ref)
reg [25:0]counter; // <=== Count register made to hold up to 50000000
(50MHz)

always @(posedge clk) //Starts on the positive edge of the clock cycle
begin
if (count == 50000000) // <=== Checks if a second has gone by
count = 0; // <=== Resets the counter
led = ~led; // <=== Changes state of led to inverse
else // <=== Second has not gone by, continue to add to counter
counter = counter + 1; // Add 1 to the counter
end

endmodule;



Hopefully that should help you as well. Feel free to email me with
BASIC questions as I have just started too, but me be more willing to
answer more simple questions then some of the pro's here, all tho they
still do an awesome job!

-Mark

 

[weizbox]

glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote in message news:<A9Mcd.490589$8_6.8672@attbi_s04>...

uzma wrote:

Hi Mark

thanx alot but the problem i m facing now is that there is an error in the
simultion ie

near "else" expecting IDENT

i m unable to comprehend it will u plz help in this regard

I think that means a ; is in the wrong place.

A good guess, anyway. I don't have problems with it quite
as often as I should, but end doesn't have a ; after it.
(Compared to PL/I where it does.)

-- glen

Forgot to place the begin/end in there.


always @(posedge clk) //Starts on the positive edge of the clock cycle
begin
if (count == 50000000) // <=== Checks if a second has gone by
begin
count = 0; // <=== Resets the counter
led = ~led; // <=== Changes state of led to inverse
end
else // <=== Second has not gone by, continue to add to counter
counter = counter + 1; // Add 1 to the counter
end

I think this should fix the problem.