New version of HDLmaker available

[B. Joshua Rosen]

I've just released a new version of HDLmaker. I've added support for the
Xilinx 6.1 tools including project generation and I've added a comment
feature to the .pin files which allows you to add comments to ports.

Example,

In the .pin file
IB_STAT_RX_LINK_ELP type = out,comment = "End of Link Packet";

Generated Verilog
//-- End of Link Packet
output IB_STAT_RX_LINK_ELP;


HDLmaker generates hierarchical Verilog and VHDL as well as scripts and
constraint files for all of the better know simulators, synthesis tools
and FPGA tool sets.

You can get HDLmaker from,

http://www.polybus.com/hdlmaker/users_guide/

It's free with a BSD style license.