New to VHDL for Xilinx

[James Williams]

Hello,

I am just learning how to program using VHDL language. I am trying to
figure out how I can generate a device which detects when two signals change
state at the same time. Below is a timing diagram. It must be able to
detect whether both signals changed state in the same time.
________
A: \_____________
_____________
B:________/
^--- I need to detect this state change.

What is the best approach for this and how would it look in VHDL?

Thanks,


James

 

[Peter Alfke]

James, in the physical world there is no "at the same time".
You have so say " within x picoseconds or nanoseconds or microseconds or milliseconds"
And you should also specify a tolerance on the accuracy of your window...

In a pracical circuit implementation, you could run the B signal through
a chain of cascaded LUTs, each also having its own flip-flop, clocked by A.
After the A transition, you can observe the flip-flops and see whether a
B signal change was travelling through the LUT chain.
If you want finer resolution than about 0.5 ns, you can use the carry
chain and achieve a resolution of 50 picoseconds.
But first you have to figure out the meaning of "simultaneous"!
Peter Alfke, Xilinx Applications
====================================
James Williams wrote:

Hello,

I am just learning how to program using VHDL language. I am trying to
figure out how I can generate a device which detects when two signals change
state at the same time. Below is a timing diagram. It must be able to
detect whether both signals changed state in the same time.
________
A: \_____________
_____________
B:________/
^--- I need to detect this state change.

What is the best approach for this and how would it look in VHDL?

Thanks,

James

 

[rickman]

James Williams wrote:

Hello,

I am just learning how to program using VHDL language. I am trying to
figure out how I can generate a device which detects when two signals change
state at the same time. Below is a timing diagram. It must be able to
detect whether both signals changed state in the same time.

A: -------|_____________

B:________|-------------
^--- I need to detect this state change.

What is the best approach for this and how would it look in VHDL?

How do you define "at the same time"? This would imply that there is an
instant in which the transition is made. In reality the transition
takes an amount of time, during which the voltage that represents the
logic state goes from one valid range, through the invalid range to the
other valid range. So there is a grey area in both time and voltage
where you don't actually know if the signal is a 1 or a 0.

If you can work though that issue, the logic required would need a
memory (FF) to know the past state of the signals. If you see that
either signal has changed state, but the XOR of the two signals has not
changed state, then you know that both inputs have changed state.

So the next question is, exactly what do you need as an output? This is
not a typical circuit needed in a typical design. So exactly how it
will be implemented will depend on just what you are looking for as an
output (how you plan to use it).

This also sounds like a homework problem. I expect the assignment is
not to design a circuit since any circuit for this will be full of
hazards. More likely this is to make you think about the problems in
such a circuit.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[James Williams]

This is to detect the negotiation phase of the IEEE 1284 parrallel port.

I will use the output to disable the current active communications mode, and
begin a negation phase to determine and set a new mode of operation. I must
detect the changes of both of these signals because they are also used for
compatibility mode and EPP mode tranfer opperations, but they don't
transistion at the same time when in commucations mode. The transition of
these two signals at near the same time only occurs at the negotiation
phase.

Regards,

James.

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F707610.FD7BBB09@yahoo.com...

James Williams wrote:

Hello,

I am just learning how to program using VHDL language. I am trying to
figure out how I can generate a device which detects when two signals
change
state at the same time. Below is a timing diagram. It must be able to
detect whether both signals changed state in the same time.

A: -------|_____________

B:________|-------------
^--- I need to detect this state change.

What is the best approach for this and how would it look in VHDL?

How do you define "at the same time"? This would imply that there is an
instant in which the transition is made. In reality the transition
takes an amount of time, during which the voltage that represents the
logic state goes from one valid range, through the invalid range to the
other valid range. So there is a grey area in both time and voltage
where you don't actually know if the signal is a 1 or a 0.

If you can work though that issue, the logic required would need a
memory (FF) to know the past state of the signals. If you see that
either signal has changed state, but the XOR of the two signals has not
changed state, then you know that both inputs have changed state.

So the next question is, exactly what do you need as an output? This is
not a typical circuit needed in a typical design. So exactly how it
will be implemented will depend on just what you are looking for as an
output (how you plan to use it).

This also sounds like a homework problem. I expect the assignment is
not to design a circuit since any circuit for this will be full of
hazards. More likely this is to make you think about the problems in
such a circuit.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[James Williams]

A(C3) Is active high, I.E I am interested in the rising edge.
B(C1) Is active low, IE I am interested in the trailing edge (High to low
transition).

Lets make Q1 and Q2 the outputs with one addition output called NEG which is
latched high only when A's rising edge is detected when B's falling edge is
detected. Something like the following C puersudeo code.

//ON Rising (A) OR trailing (B)
bool APrev,BPrev;
APrev=A;
BPrev=B;
while(1)
{
if(RisingEdge(A) && A=true&& BPrev !=B)
{
NEG=true;

}
elseif(TrailingEdge(B) && (A==APrev) && A==true)
{
//Nibble read
ReadNibble();
}
elseif(Trailing(B) && A!=true)
{
CompatibilityWrite();
}
BPrev = B;
APrev= A;
}

Anyway, something like this.

Regards,

James


"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F7092CD.48DC74CF@yahoo.com...

Did my answer help you? I understand what you are tying to do, but your
description still is not clear enough to tell me exactly what you want
for an output.

Can you define exactly the state of the two signals at this point? Will
one always be low going high or will it vary?


James Williams wrote:

This is to detect the negotiation phase of the IEEE 1284 parrallel port.

I will use the output to disable the current active communications mode,
and
begin a negation phase to determine and set a new mode of operation. I
must
detect the changes of both of these signals because they are also used
for
compatibility mode and EPP mode tranfer opperations, but they don't
transistion at the same time when in commucations mode. The transition
of
these two signals at near the same time only occurs at the negotiation
phase.

Regards,

James.

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F707610.FD7BBB09@yahoo.com...
James Williams wrote:

Hello,

I am just learning how to program using VHDL language. I am trying
to
figure out how I can generate a device which detects when two
signals
change
state at the same time. Below is a timing diagram. It must be able
to
detect whether both signals changed state in the same time.

A: -------|_____________

B:________|-------------
^--- I need to detect this state change.

What is the best approach for this and how would it look in VHDL?

How do you define "at the same time"? This would imply that there is
an
instant in which the transition is made. In reality the transition
takes an amount of time, during which the voltage that represents the
logic state goes from one valid range, through the invalid range to
the
other valid range. So there is a grey area in both time and voltage
where you don't actually know if the signal is a 1 or a 0.

If you can work though that issue, the logic required would need a
memory (FF) to know the past state of the signals. If you see that
either signal has changed state, but the XOR of the two signals has
not
changed state, then you know that both inputs have changed state.

So the next question is, exactly what do you need as an output? This
is
not a typical circuit needed in a typical design. So exactly how it
will be implemented will depend on just what you are looking for as an
output (how you plan to use it).

This also sounds like a homework problem. I expect the assignment is
not to design a circuit since any circuit for this will be full of
hazards. More likely this is to make you think about the problems in
such a circuit.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the
XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX