New release of HDLmaker

[General Schvantzkoph]

I've put a new release of hdlmaker on the web,

http://www.polybus.com/hdlmaker/users_guide/index.htm

HDLmaker generates Verilog, VHDL as well as simulation and synthesis
scripts. This version has a few new features, support of the latest Altera
and Xilinx FPGAs. It also supports Actel and Achronix FPGAs.

HDLmaker is free software, it's licensed under the BSD.

 

[General Schvantzkoph]

On Thu, 16 Sep 2010 17:25:26 -0700, OutputLogic wrote:

Hi,

It'd be very convenient to post the manual in PDF or HTML format online
instead of requiring tool installation.

Thanks,
Evgeni

The manual is online. I admit that it's pretty mediocre, one of these
days I'll take the time to rewrite it.

http://www.polybus.com/hdlmaker/users_guide/id20.htm

http://www.polybus.com/hdlmaker/users_guide/id18.htm

 

[OutputLogic]

Hi,

It'd be very convenient to post the manual in PDF or HTML format
online instead of requiring tool installation.

Thanks,
Evgeni

 

[General Schvantzkoph]

On Fri, 17 Sep 2010 07:20:41 -0700, rickman wrote:

On Sep 16, 8:40 pm, General Schvantzkoph <schvantzk...@yahoo.com> wrote:
On Thu, 16 Sep 2010 17:25:26 -0700, OutputLogic wrote:
Hi,

It'd be very convenient to post the manual in PDF or HTML format
online instead of requiring tool installation.

Thanks,
Evgeni

The manual is online. I admit that it's pretty mediocre, one of these
days I'll take the time to rewrite it.

http://www.polybus.com/hdlmaker/users_guide/id20.htm

http://www.polybus.com/hdlmaker/users_guide/id18.htm

Rather than make me read a mediocre manual, can you briefly describe
this software? What are the inputs to allow HDL to be generated?

Rick

HDLmaker sources are .top files which instantiate components and contains
directives for various tools and the .pin file which specify ports as
well as pin numbers, logic levels, io sets and resets, io registering,
and timing constraints. HDLmaker has a C like language which allows you
to calculate signal names, parameter values, conditional operations and
loops. The output of HDLmaker is either Verilog or VHDL (depending on a
switch). It has extensive support for Xilinx and Altera tools as well as
Synplify. It generates Make files for Modelsim/Questa and filelists for
NC and VCS. It generates UCF and SDC constraint files, Quartus Projects,
XST scripts. It also has support for Xilinx floorplanning (you can
generate floor plans using it's C like language.

Where ever possible it uses common directives that are portable across
tools, for example the #clock command defines clocks, it generates the
appropriate constraints and directives for Xilinx, Altera, Synplify and
Precision. In addition to generic directives there are directives that
are specific to a tool like XST or Quartus. A design that's written in
HDLmaker is easily portable between tools and technologies and even
languages.

One of it's main features is that it automatically connects ports as long
as the port names are the same, i.e. port foo on modules X and Y will be
connected without having to specify it in the code. If you want to
connect a port to a different signal or bus then you use the connect
statement. Signal names and numbers can be calculated if you want,
HDlmaker does both integer and string arithmetic (for example "foo_a" + 2
becomes foo_c in the generated code, concatenations and integer and
string variables are also supported).

There are a number of examples on the web,

http://www.polybus.com/hdlmaker/users_guide/id25.htm

I think I'll add a few more examples in the next few weeks which
illustrate some of HDLmakers newer features.

 

[rickman]

On Sep 16, 8:40 pm, General Schvantzkoph <schvantzk...@yahoo.com>
wrote:

On Thu, 16 Sep 2010 17:25:26 -0700, OutputLogic wrote:
Hi,

It'd be very convenient to post the manual in PDF or HTML format online
instead of requiring tool installation.

Thanks,
Evgeni

The manual is online. I admit that it's pretty mediocre, one of these
days I'll take the time to rewrite it.

http://www.polybus.com/hdlmaker/users_guide/id20.htm

http://www.polybus.com/hdlmaker/users_guide/id18.htm

Rather than make me read a mediocre manual, can you briefly describe
this software? What are the inputs to allow HDL to be generated?

Rick

 

[rickman]

On Sep 17, 11:19 am, General Schvantzkoph <schvantzk...@yahoo.com>
wrote:

On Fri, 17 Sep 2010 07:20:41 -0700, rickman wrote:
On Sep 16, 8:40 pm, General Schvantzkoph <schvantzk...@yahoo.com> wrote:
On Thu, 16 Sep 2010 17:25:26 -0700, OutputLogic wrote:
Hi,

It'd be very convenient to post the manual in PDF or HTML format
online instead of requiring tool installation.

Thanks,
Evgeni

The manual is online. I admit that it's pretty mediocre, one of these
days I'll take the time to rewrite it.

http://www.polybus.com/hdlmaker/users_guide/id20.htm

http://www.polybus.com/hdlmaker/users_guide/id18.htm

Rather than make me read a mediocre manual, can you briefly describe
this software? What are the inputs to allow HDL to be generated?

Rick

HDLmaker sources are .top files which instantiate components and contains
directives for various tools and the .pin file which specify ports as
well as pin numbers, logic levels, io sets and resets, io registering,
and timing constraints. HDLmaker has a C like language which allows you
to calculate signal names, parameter values, conditional operations and
loops. The output of HDLmaker is either Verilog or VHDL (depending on a
switch). It has extensive support for Xilinx and Altera tools as well as
Synplify. It generates Make files for Modelsim/Questa and filelists for
NC and VCS. It generates UCF and SDC constraint files, Quartus Projects,
XST scripts. It also has support for Xilinx floorplanning (you can
generate floor plans using it's C like language.

Where ever possible it uses common directives that are portable across
tools, for example the #clock command defines clocks, it generates the
appropriate constraints and directives for Xilinx, Altera, Synplify and
Precision. In addition to generic directives there are directives that
are specific to a tool like XST or Quartus. A design that's written in
HDLmaker is easily portable between tools and technologies and even
languages.

One of it's main features is that it automatically connects ports as long
as the port names are the same, i.e. port foo on modules X and Y will be
connected without having to specify it in the code. If you want to
connect a port to a different signal or bus then you use the connect
statement. Signal names and numbers can be calculated if you want,
HDlmaker does both integer and string arithmetic (for example "foo_a" + 2
becomes foo_c in the generated code, concatenations and integer and
string variables are also supported).

There are a number of examples on the web,

http://www.polybus.com/hdlmaker/users_guide/id25.htm

I think I'll add a few more examples in the next few weeks which
illustrate some of HDLmakers newer features.

So let me make sure I understand. HDLmaker allows us to program in
its own special language that is C like and largely structural rather
than programming in HDL both structurally specifying logic and/or
inferring logic.

What is better about this than coding in HDL? I don't get why you are
touting how your tool works with all brands. HDL by design is vendor
and device and in fact, technology independent. Most of what you list
above is not anything HDL doesn't do or that I would need to do.

Am I missing the point?

Rick

 

[General Schvantzkoph]

On Fri, 17 Sep 2010 14:04:42 -0700, rickman wrote:

On Sep 17, 11:19 am, General Schvantzkoph <schvantzk...@yahoo.com
wrote:
On Fri, 17 Sep 2010 07:20:41 -0700, rickman wrote:
On Sep 16, 8:40 pm, General Schvantzkoph <schvantzk...@yahoo.com
wrote:
On Thu, 16 Sep 2010 17:25:26 -0700, OutputLogic wrote:
Hi,

It'd be very convenient to post the manual in PDF or HTML format
online instead of requiring tool installation.

Thanks,
Evgeni

The manual is online. I admit that it's pretty mediocre, one of
these days I'll take the time to rewrite it.

http://www.polybus.com/hdlmaker/users_guide/id20.htm

http://www.polybus.com/hdlmaker/users_guide/id18.htm

Rather than make me read a mediocre manual, can you briefly describe
this software? What are the inputs to allow HDL to be generated?

Rick

HDLmaker sources are .top files which instantiate components and
contains directives for various tools and the .pin file which specify
ports as well as pin numbers, logic levels, io sets and resets, io
registering, and timing constraints. HDLmaker has a C like language
which allows you to calculate signal names, parameter values,
conditional operations and loops. The output of HDLmaker is either
Verilog or VHDL (depending on a switch). It has extensive support for
Xilinx and Altera tools as well as Synplify. It generates Make files
for Modelsim/Questa and filelists for NC and VCS. It generates UCF and
SDC constraint files, Quartus Projects, XST scripts. It also has
support for Xilinx floorplanning (you can generate floor plans using
it's C like language.

Where ever possible it uses common directives that are portable across
tools, for example the #clock command defines clocks, it generates the
appropriate constraints and directives for Xilinx, Altera, Synplify and
Precision. In addition to generic directives there are directives that
are specific to a tool like XST or Quartus. A design that's written in
HDLmaker is easily portable between tools and technologies and even
languages.

One of it's main features is that it automatically connects ports as
long as the port names are the same, i.e. port foo on modules X and Y
will be connected without having to specify it in the code. If you want
to connect a port to a different signal or bus then you use the connect
statement. Signal names and numbers can be calculated if you want,
HDlmaker does both integer and string arithmetic (for example "foo_a" +
2 becomes foo_c in the generated code, concatenations and integer and
string variables are also supported).

There are a number of examples on the web,

http://www.polybus.com/hdlmaker/users_guide/id25.htm

I think I'll add a few more examples in the next few weeks which
illustrate some of HDLmakers newer features.

So let me make sure I understand. HDLmaker allows us to program in its
own special language that is C like and largely structural rather than
programming in HDL both structurally specifying logic and/or inferring
logic.

What is better about this than coding in HDL? I don't get why you are
touting how your tool works with all brands. HDL by design is vendor
and device and in fact, technology independent. Most of what you list
above is not anything HDL doesn't do or that I would need to do.

Am I missing the point?

Rick

When I started writing HDLmaker in the early 90's Verilog didn't have any
generate capabilities and even today it's much less capable then HDLmaker.
In addition to generating code HDLmaker does the following automatically,

1) It generates project files, scripts, make files and constraint files for lots of different
tools. Once a design is in HDLmaker you can move from one tool to another
in seconds.

2) It builds the structure with minimum coding. In the most extreme case
where all of the ports on the leaf modules have corresponding names all
you have to do is list the components, for example,

#insert "foo.v";

#insert "bar.v";

#insert "more.top";

3) You can parametrize a design

#for(i=0;i<num_lanes;i++)
{
#assign vl = "_a" + i;
#assign lane = "lane_a" + i;
#assign credit = "credit_level" $ vl;

#insert "ib_link_ctrl_fctrl_lane.v",name = "fctrl_lane_",
#parameter VIRTUAL_LANE = i,
connect IB_CREDIT_LEVEL[12:0] = #credit[12:0],
connect IB_FLOW_CTRL_TIMEOUT = IB_FLOW_CTRL_TIMEOUT[#i],
connect IB_STAT_RX_ABR_ERR = rx_abr_err[#i],
connect IB_TX_CREDIT_AVAIL = IB_TX_CREDIT_AVAIL[#i],
connect IB_TX_CREDIT_OK = IB_TX_CREDIT_OK[#i],
connect flow_ctrl_violation = flow_ctrl_violation[#i],
connect high_priority_request = high_priority_request[#i],
connect lane[3:0] = #lane[3:0],
connect lane_operational = lane_operational[#i],
connect link_packet_ready = link_packet_ready,
connect link_packet_valid = link_packet_valid,
connect link_packet_vl[3:0] = link_packet_vl[3:0],
connect rx_abr[31:0] = "rx_abr" $ vl[31:0],
connect nxt_flow_ctrl_packet[31:0] = "nxt_flow_ctrl_packet" $ vl[31:0],
connect shadow_credit_near_empty = shadow_credit_near_empty[#i];
}

4) It's really easy to create your entire structure up front. All you have to do
is define the pin files and the top files for each level. HDLmaker tells you if
there are any undriven inputs or outputs or bus conflicts.

Here of a pin file. HDLmaker generates the ports of a module from this, including
the comments.

#nopadring
#pins
IB_LINK_STATE[2:0] type = in, comment = "Link State, see Vol 1, section 7.2 of the IBA spec
0 LINK_DOWN
1 LINK_INIT
2 LINK_ARM
3 LINK_ACTIVE
4 LINK_ACT_DEFER";

DLANE_OFFSET[2:0] type = in,comment = "Base Virtual Lane";
IB_BUFFER_SIZE[11:0] type = in, comment = "Buffer space in 64 byte credits";
IB_BUFFER_SIZE_REQ[3:0] type = out,comment = "VL of the free space request";
IB_BUFFER_SIZE_REQ_VALID type = out,comment = "Request free space in VL buffer";
IB_BUFFER_SIZE_VALID type = in,comment = "Buffer size valud is valid";
IB_BUFFER_SIZE_VL[3:0] type = in,comment = "VL of buffer space value";
#endpins

5) It generates both Verilog and VHDL code so you can reuse code in both environment.

6) For the top level of an FPGA you can specify all aspects of the pins in a single file.

#uselibrary
#pins
REF_CLK type = in,logic = PASS,iostandard="1.4-V PCML",input_term = "OCT_100_ohms",comment = "625MHz reference 312",pin = [AL38];

SD_TX[3:0] type = out,logic = "PASS",comment = "SerDes serial out",iostandard="1.4-V PCML",output_term="OCT 100 OHMS",pin=[AD36,AB36,T36,P36];
SD_RX[3:0] type = in,logic = "PASS",comment = "SerDes Serial in",iostandard="1.4-V PCML",input_term="OCT 100 OHMS",pin=[AE38,AC38,U38,R38];
PARAM_SEL[7:0] type = in,comment = "LSBs of the LID, from switches",pin= [AM26,AN26,AP26,AN27,AP27,AT27,AU27,AW27];
gblreset_l type = in,comment = "Global Async reset",pin=AW18;
#endpins

This will generate not only the Verilog or VHDL for the top level module
and the pad ring module but it will also generate the constraint files
(ucf for Xilinx, the Quartus project file for Altera).

7) Making changes are really easy, mostly all you have to do is make the changes in the leaf modules,
the structural code is generated by HDLmaker.

8) Coping tool directives from one project to another is easier because
you just have to copy a few lines from a text file. Here are the Quartus
directives from one of my projects,


#beneficial_skew_opt 1;
#combo_logic_for_area 1;
#equiv_logic_removal 0;
#fitter_aggressive_mode "automatically";
#gen_mif 1;
#hold_timing_min_tpd 1;
#mux_restructure 1;
#placement_effort 4;
#register_balancing "yes";
#register_duplication 1;
#remove_duplicate_logic 0;
#rom_recognition 1;
#router_effort 3;
#smart_recompile 0;
#verilog2001 "yes";
#timequest 1;
#signal_tap "demo.stp";
#derive_clocks;

Here is the Quartus project that HDLmaker generated for this design,

# Quartus project file, Generated by HDLmaker Rev 9.3.7
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.0"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "Sept 17, 2010"
set_global_assignment -name LAST_QUARTUS_VERSION "10.0"
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/fpga_defs.vh
set_global_assignment -name VERILOG_FILE ../../../reference_designs/aqdr_link_layer/altera/s4gx/v/s4gt_demo_625.v
set_global_assignment -name VERILOG_FILE ../../../unit_tests/aqdr_link_layer/common/v/aqdr_traffic_gen.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/fpga/s4gx/v/s4gt_aqdr_link_625.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/top_level/v/aqdr_pcs_link_fpga_10b.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/top_level/v/aqdr_ib_link_layer.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_control.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_clk_ctrl.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/control/init_and_training/v/aqdr_ib_link_ctrl_init_training.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/control/link_state/v/aqdr_ib_link_ctrl_state_machine.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/flow_control/vlanes_8/v/aqdr_ib_link_multilane_fctrl.v
set_global_assignment -name VERILOG_FILE ../../../common/crc/v/CRC16_D32.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/flow_control/common/v/aqdr_ib_link_ctrl_fctrl_common.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/flow_control/common/v/aqdr_ib_link_ctrl_fctrl_lane.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/receiver/common/v/aqdr_ib_link_receiver.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/receiver/crc/v/aqdr_ib_link_rx_crc.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/crc/v/aqdr_ib_rx_icrc_generator.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/crc/v/aqdr_ib_rx_icrc_mask.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/crc/v/aqdr_rx_crc32x128.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/crc/v/aqdr_rx_crc16x128.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_datapath.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_assembler.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_datapipe.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_stage.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/receiver/status/v/aqdr_ib_link_rx_status.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/transmitter/common/v/aqdr_ib_link_transmitter.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/transmitter/crc/v/aqdr_ib_link_xmit_crc_gen.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/crc/v/aqdr_ib_icrc_generator_128.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/crc/v/aqdr_ib_icrc_mask.v
set_global_assignment -name VERILOG_FILE ../../../common/crc/v/pb_tx_crc32x128.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/crc/v/aqdr_ib_vcrc_generator_128.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/crc/v/aqdr_ib_vcrc_ctrl.v
set_global_assignment -name VERILOG_FILE ../../../common/crc/v/pb_crc16x128.v
set_global_assignment -name VERILOG_FILE ../../../common/crc/v/pb_crc16x32.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_xmit_dpath.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_tx_mux.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_xmit_ctrl.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_xmit_status.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/dregce_sr.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/top_level/v/aqdr_pcs_wide_10b.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/top_level/v/aqdr_pcs_wide_8b.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/top_level/v/aqdr_pcs_reset.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_wide.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_align_wide.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/receiver/v/aqdr_pcs_alignment_buffer.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_ctrl.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_mux2x1.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_offset_reg.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_swap_wide.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_swap_ctrl.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_regmux2x1.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_training_wide.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_training_ctrl.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_training_lane_wide.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_fifo_deserializer1x4.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/receiver/v/pcs_rx_loopback.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_async_fifo.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_cmux2x1.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_match_ab.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/receiver/v/pcs_rx_lpbk_ctrl.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/buffer.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/transmitter/v/pcs_tx_wide.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/pcs/v/aqdr_pcs_tx_idle_gen_wide.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/pcs/v/aqdr_link_idle_gen.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/transmitter/v/aqdr_pcs_tx_swap.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_mux4x1.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_mux8x1.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/transmitter/v/pcs_tx_buffer_wide.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_async_fifo_early_wr.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_fifo_serializer4x1.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_or_reduction.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_packet_packer.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/transmitter/v/pcs_tx_decode.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/transmitter/v/pcs_tx_datapath_wide.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/transmitter/v/aqdr_pcs_tx_lane.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/transmitter/v/pcs_tx_ctrl.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/transmitter/v/pcs_tx_input_ctrl.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_base_x_decode_wide_4x.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_base_x_decode_wide.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_comma_align.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_decode_8b10b.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_decode_8b10b_ctrl.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_base_x_encode_wide_4x.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_base_x_encode_wide.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_encode_8b10b.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_igate.v
set_global_assignment -name VERILOG_FILE ../../../common/s4gx/v/s4gt_sd_qdr_625.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_dreg.v
set_global_assignment -name VERILOG_FILE ../../../common/s4gx/v/s4gt_625_rom.v
set_global_assignment -name VERILOG_FILE ../../../common/s4gx/v/s4gt_wide_qdr_625.v
set_global_assignment -name VERILOG_FILE ../../../common/s4gx/v/s4gx_config_ctrl_4x.v
set_global_assignment -name VERILOG_FILE ../../../common/s4gx/v/s4gx_reconfig.v
set_global_assignment -name VERILOG_FILE ../../../common/s4gx/v/s4gt_clk_260_625_ref.v
set_global_assignment -name VERILOG_FILE ../../../reference_designs/aqdr_link_layer/altera/s4gx/v/s4gt_demo_625_pads.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/PB_IBUF.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/PB_OBUF.v

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name SAFE_STATE_MACHINE ON
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION AUTOMATICALLY
set_global_assignment -name REMOVE_DUPLICATE_LOGIC OFF
set_global_assignment -name PARALLEL_SYNTHESIS ON
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name AUTO_ROM_RECOGNITION ON
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
set_global_assignment -name STATE_MACHINE_PROCESSING AUTO
set_global_assignment -name MUX_RESTRUCTURE ON
set_global_assignment -name AUTO_RESOURCE_SHARING ON
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 1517
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 2
set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001
set_global_assignment -name FAMILY "STRATIX IV"
set_global_assignment -name TOP_LEVEL_ENTITY s4gt_demo_625
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF

# Fitter Assignments
# ==================
set_global_assignment -name OPTIMIZE_FAST_CORNER_TIMING ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_instance_assignment -name MAX_FANOUT "32" -to *
set_global_assignment -name ROUTER_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name DEVICE EP4S100G2F40i2
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name OPTIMIZE_TIMING "EXTRA EFFORT"
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION ON
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 3
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 4
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_GATE_RETIME ON

# -------------------
# start CLOCK(REF_CLK)

set_global_assignment -name FMAX_REQUIREMENT "630 MHz" -section_id REF_CLK
set_global_assignment -name DUTY_CYCLE 50 -section_id REF_CLK

# end CLOCK(REF_CLK)
# -----------------
set_global_assignment -name ENABLE_DRC_SETTINGS ON
set_global_assignment -name ENABLE_CLOCK_LATENCY ON
set_global_assignment -name SMART_RECOMPILE OFF
set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS ON
set_global_assignment -name IGNORE_LCELL_BUFFERS ON
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS OFF
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "NORMAL COMPILATION"
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
set_global_assignment -name SDC_FILE ../constraints/s4gt_demo_625.sdc
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name SDC_FILE ../constraints/s4gt_demo_625.sdc
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF ON
set_global_assignment -name SAVE_DISK_SPACE ON
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS OFF
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
set_global_assignment -name SIGNALTAP_FILE ../../../reference_designs/aqdr_link_layer/altera/s4gx/constraints/demo.stp
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name USE_SIGNALTAP_FILE ../../../reference_designs/aqdr_link_layer/altera/s4gx/constraints/demo.stp
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name EDA_SIMULATION_TOOL "NC-Verilog (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "100 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY ON -section_id eda_simulation
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS ON -section_id eda_simulation
set_location_assignment PIN_AW27 -to PARAM_SEL_pin[0]
set_location_assignment PIN_AU27 -to PARAM_SEL_pin[1]
set_location_assignment PIN_AT27 -to PARAM_SEL_pin[2]
set_location_assignment PIN_AP27 -to PARAM_SEL_pin[3]
set_location_assignment PIN_AN27 -to PARAM_SEL_pin[4]
set_location_assignment PIN_AP26 -to PARAM_SEL_pin[5]
set_location_assignment PIN_AN26 -to PARAM_SEL_pin[6]
set_location_assignment PIN_AM26 -to PARAM_SEL_pin[7]
set_location_assignment PIN_AL38 -to REF_CLK
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to REF_CLK
set_instance_assignment -name INPUT_TERMINATION "OCT_100_OHMS" -to REF_CLK
set_location_assignment PIN_R38 -to SD_RX[0]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_RX[0]
set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to SD_RX[0]
set_location_assignment PIN_U38 -to SD_RX[1]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_RX[1]
set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to SD_RX[1]
set_location_assignment PIN_AC38 -to SD_RX[2]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_RX[2]
set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to SD_RX[2]
set_location_assignment PIN_AE38 -to SD_RX[3]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_RX[3]
set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to SD_RX[3]
set_location_assignment PIN_P36 -to SD_TX[0]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_TX[0]
set_instance_assignment -name OUTPUT_TERMINATION "OCT 100 OHMS" -to SD_TX[0]
set_location_assignment PIN_T36 -to SD_TX[1]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_TX[1]
set_instance_assignment -name OUTPUT_TERMINATION "OCT 100 OHMS" -to SD_TX[1]
set_location_assignment PIN_AB36 -to SD_TX[2]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_TX[2]
set_instance_assignment -name OUTPUT_TERMINATION "OCT 100 OHMS" -to SD_TX[2]
set_location_assignment PIN_AD36 -to SD_TX[3]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_TX[3]
set_instance_assignment -name OUTPUT_TERMINATION "OCT 100 OHMS" -to SD_TX[3]
set_location_assignment PIN_AW18 -to gblreset_l_pin
set_location_assignment PIN_AN30 -to led_its_alive_pin
set_location_assignment PIN_AV29 -to led_link_active_pin
set_location_assignment PIN_AT29 -to led_link_ddr_pin
set_location_assignment PIN_AU29 -to led_link_qdr_pin
set_location_assignment PIN_AP30 -to led_link_rx_error_pin
set_location_assignment PIN_AW29 -to led_link_up_pin
set_location_assignment PIN_AW30 -to led_loopback_pin
set_location_assignment PIN_AT30 -to led_pass_pin

###############################################################
Here is the Modelsim Make file that HDLmaker generated for this project


VLOG_ARG_FILES = \
v/fpga.defs \
v/idle.defs



VLOG_ARGS = \
-f v/fpga.defs \
-f v/idle.defs


MODEL_OBJS = \
work/tcstat \
work/ib_rxtbmux \
work/par_gen \
work/par_txlanemux \
work/par_traffic_scheduler \
work/par_scheduler \
work/ib_idlegen \
work/ib_idlemon1 \
work/ib_idlemon \
work/ib_lts \
work/lts_timer \
work/packet_gen \
work/ib_fcgen \
work/ib_linkgen \
work/ib_txlanemux \
work/ib_traffic_scheduler \
work/ib_linkscheduler \
work/ib_phygen \
work/ib_lphygen \
work/ib_scheduler \
work/packet_mon \
work/ib_phymon \
work/ib_rxsm \
work/tb_parameters \
work/status_tb \
work/pb_rmux2x1 \
work/pb_mux4x1 \
work/pb_mux2x1 \
work/pb_dreg \
work/pb_buffer \
work/par_txbfm \
work/par_rxbfm \
work/par_tb \
work/ib_txbfm \
work/ib_rxbfm \
work/ib_clkdivider \
work/ib_tsmonall \
work/ib_tsmon \
work/ib_busphymon \
work/ib_tb \
work/glbl \
work/delayline \
work/ctrl_tb \
work/clk_1000mhz \
work/pcs_tx_input_ctrl \
work/pcs_tx_ctrl \
work/aqdr_pcs_tx_lane \
work/pcs_tx_datapath_wide \
work/pcs_tx_decode \
work/pb_packet_packer \
work/pb_or_reduction \
work/pb_fifo_serializer4x1 \
work/pb_async_fifo_early_wr \
work/pcs_tx_buffer_wide \
work/pb_mux8x1 \
work/aqdr_pcs_tx_swap \
work/aqdr_link_idle_gen \
work/aqdr_pcs_tx_idle_gen_wide \
work/pcs_tx_wide \
work/buffer \
work/pcs_rx_lpbk_ctrl \
work/pb_match_ab \
work/pb_cmux2x1 \
work/pb_async_fifo \
work/pcs_rx_loopback \
work/pb_fifo_deserializer1x4 \
work/aqdr_pcs_rx_training_lane_wide \
work/aqdr_pcs_rx_training_ctrl \
work/aqdr_pcs_rx_training_wide \
work/pb_regmux2x1 \
work/aqdr_pcs_rx_swap_ctrl \
work/aqdr_pcs_rx_swap_wide \
work/pb_offset_reg \
work/aqdr_pcs_rx_ctrl \
work/aqdr_pcs_alignment_buffer \
work/aqdr_pcs_rx_align_wide \
work/aqdr_pcs_rx_wide \
work/aqdr_pcs_reset \
work/aqdr_pcs_wide_8b \
work/dregce_sr \
work/aqdr_ib_link_xmit_status \
work/aqdr_ib_link_xmit_ctrl \
work/aqdr_ib_link_tx_mux \
work/aqdr_ib_link_xmit_dpath \
work/pb_crc16x32 \
work/pb_crc16x128 \
work/aqdr_ib_vcrc_ctrl \
work/aqdr_ib_vcrc_generator_128 \
work/pb_tx_crc32x128 \
work/aqdr_ib_icrc_mask \
work/aqdr_ib_icrc_generator_128 \
work/aqdr_ib_link_xmit_crc_gen \
work/aqdr_ib_link_transmitter \
work/aqdr_ib_link_rx_status \
work/aqdr_ib_link_rx_stage \
work/aqdr_ib_link_rx_datapipe \
work/aqdr_ib_link_rx_assembler \
work/aqdr_ib_link_rx_datapath \
work/aqdr_rx_crc16x128 \
work/aqdr_rx_crc32x128 \
work/aqdr_ib_rx_icrc_mask \
work/aqdr_ib_rx_icrc_generator \
work/aqdr_ib_link_rx_crc \
work/aqdr_ib_link_receiver \
work/aqdr_ib_link_ctrl_fctrl_lane \
work/aqdr_ib_link_ctrl_fctrl_common \
work/CRC16_D32 \
work/aqdr_ib_link_multilane_fctrl \
work/aqdr_ib_link_ctrl_state_machine \
work/aqdr_ib_link_ctrl_init_training \
work/aqdr_ib_link_clk_ctrl \
work/aqdr_ib_link_control \
work/aqdr_ib_link_layer \
work/aqdr_pcs_link_fpga_8b \
work/fpga_defs \
work/ibtb_top \
work/idle_defs \
work


all: $(MODEL_OBJS)


work:
vlib work


clean:
rm -Rf work
vlib work


work/idle_defs: ../../fpga_qdr/v/idle_defs.vh $(VLOG_ARG_FILES)
vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS) ../../fpga_qdr/v/idle_defs.vh
touch work/idle_defs

work/ibtb_top: ../../../../testbench/aqdr_link_layer/fpga_qdr/v/ibtb_top.v $(VLOG_ARG_FILES)
vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS) ../../../../testbench/aqdr_link_layer/fpga_qdr/v/ibtb_top.v
touch work/ibtb_top

work/fpga_defs: ../../../../common/hdlmaker/v/fpga_defs.vh $(VLOG_ARG_FILES)
vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS) ../../../../common/hdlmaker/v/fpga_defs.vh
touch work/fpga_defs

work/aqdr_pcs_link_fpga_8b: ../../../../cores/aqdr_link_layer/top_level/v/aqdr_pcs_link_fpga_8b.v $(VLOG_ARG_FILES)
vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS) ../../../../cores/aqdr_link_layer/top_level/v/aqdr_pcs_link_fpga_8b.v
touch work/aqdr_pcs_link_fpga_8b

work/aqdr_ib_link_layer: ../../../../cores/aqdr_link_layer/top_level/v/aqdr_ib_link_layer.v $(VLOG_ARG_FILES)
vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS) ../../../../cores/aqdr_link_layer/top_level/v/aqdr_ib_link_layer.v
touch work/aqdr_ib_link_layer

work/aqdr_ib_link_control: ../../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_control.v $(VLOG_ARG_FILES)
vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS) ../../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_control.v
touch work/aqdr_ib_link_control

work/aqdr_ib_link_clk_ctrl: ../../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_clk_ctrl.v $(VLOG_ARG_FILES)
vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS) ../../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_clk_ctrl.v
touch work/aqdr_ib_link_clk_ctrl

work/aqdr_ib_link_ctrl_init_training: ../../../../cores/aqdr_link_layer/control/init_and_training/v/aqdr_ib_link_ctrl_init_training.v $(VLOG_ARG_FILES)
vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS) ../../../../cores/aqdr_link_layer/control/init_and_training/v/aqdr_ib_link_ctrl_init_training.v
touch work/aqdr_ib_link_ctrl_init_training

work/aqdr_ib_link_ctrl_state_machine: ../../../../cores/aqdr_link_layer/control/link_state/v/aqdr_ib_link_ctrl_state_machine.v $(VLOG_ARG_FILES)
vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS) ../../../../cores/aqdr_link_layer/control/link_state/v/aqdr_ib_link_ctrl_state_machine.v
touch work/aqdr_ib_link_ctrl_state_machine

###########################################

Here is the file list that it generated for NCsim,

.../../fpga_qdr/v/idle_defs.vh
.../../../../testbench/aqdr_link_layer/fpga_qdr/v/ibtb_top.v
.../../../../common/hdlmaker/v/fpga_defs.vh
.../../../../cores/aqdr_link_layer/top_level/v/aqdr_pcs_link_fpga_8b.v
.../../../../cores/aqdr_link_layer/top_level/v/aqdr_ib_link_layer.v
.../../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_control.v
.../../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_clk_ctrl.v
.../../../../cores/aqdr_link_layer/control/init_and_training/v/aqdr_ib_link_ctrl_init_training.v
.../../../../cores/aqdr_link_layer/control/link_state/v/aqdr_ib_link_ctrl_state_machine.v
.../../../../cores/aqdr_link_layer/flow_control/vlanes_8/v/aqdr_ib_link_multilane_fctrl.v
.../../../../common/crc/v/CRC16_D32.v
.../../../../cores/aqdr_link_layer/flow_control/common/v/aqdr_ib_link_ctrl_fctrl_common.v
.../../../../cores/aqdr_link_layer/flow_control/common/v/aqdr_ib_link_ctrl_fctrl_lane.v
.../../../../cores/aqdr_link_layer/receiver/common/v/aqdr_ib_link_receiver.v
.../../../../cores/aqdr_link_layer/receiver/crc/v/aqdr_ib_link_rx_crc.v
.../../../../cores/aqdr_link_layer/crc/v/aqdr_ib_rx_icrc_generator.v
.../../../../cores/aqdr_link_layer/crc/v/aqdr_ib_rx_icrc_mask.v
.../../../../cores/aqdr_link_layer/crc/v/aqdr_rx_crc32x128.v
.../../../../cores/aqdr_link_layer/crc/v/aqdr_rx_crc16x128.v
.../../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_datapath.v
.../../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_assembler.v
.../../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_datapipe.v
.../../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_stage.v
.../../../../cores/aqdr_link_layer/receiver/status/v/aqdr_ib_link_rx_status.v
.../../../../cores/aqdr_link_layer/transmitter/common/v/aqdr_ib_link_transmitter.v
.../../../../cores/aqdr_link_layer/transmitter/crc/v/aqdr_ib_link_xmit_crc_gen.v
.../../../../cores/aqdr_link_layer/crc/v/aqdr_ib_icrc_generator_128.v
.../../../../cores/aqdr_link_layer/crc/v/aqdr_ib_icrc_mask.v
.../../../../common/crc/v/pb_tx_crc32x128.v
.../../../../cores/aqdr_link_layer/crc/v/aqdr_ib_vcrc_generator_128.v
.../../../../cores/aqdr_link_layer/crc/v/aqdr_ib_vcrc_ctrl.v
.../../../../common/crc/v/pb_crc16x128.v
.../../../../common/crc/v/pb_crc16x32.v
.../../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_xmit_dpath.v
.../../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_tx_mux.v
.../../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_xmit_ctrl.v
.../../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_xmit_status.v
.../../../../common/hdlmaker/v/dregce_sr.v
.../../../../cores/pcs_layer/top_level/v/aqdr_pcs_wide_8b.v
.../../../../cores/pcs_layer/top_level/v/aqdr_pcs_reset.v
.../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_wide.v
.../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_align_wide.v
.../../../../cores/pcs_layer/receiver/v/aqdr_pcs_alignment_buffer.v
.../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_ctrl.v
.../../../../common/hdlmaker/v/pb_offset_reg.v
.../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_swap_wide.v
.../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_swap_ctrl.v
.../../../../common/hdlmaker/v/pb_regmux2x1.v
.../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_training_wide.v
.../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_training_ctrl.v
.../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_training_lane_wide.v
.../../../../common/hdlmaker/v/pb_fifo_deserializer1x4.v
.../../../../cores/pcs_layer/receiver/v/pcs_rx_loopback.v
.../../../../common/hdlmaker/v/pb_async_fifo.v
.../../../../common/hdlmaker/v/pb_cmux2x1.v
.../../../../common/hdlmaker/v/pb_match_ab.v
.../../../../cores/pcs_layer/receiver/v/pcs_rx_lpbk_ctrl.v
.../../../../common/hdlmaker/v/buffer.v
.../../../../cores/pcs_layer/transmitter/v/pcs_tx_wide.v
.../../../../cores/aqdr_link_layer/pcs/v/aqdr_pcs_tx_idle_gen_wide.v
.../../../../cores/aqdr_link_layer/pcs/v/aqdr_link_idle_gen.v
.../../../../cores/pcs_layer/transmitter/v/aqdr_pcs_tx_swap.v
.../../../../common/hdlmaker/v/pb_mux8x1.v
.../../../../cores/pcs_layer/transmitter/v/pcs_tx_buffer_wide.v
.../../../../common/hdlmaker/v/pb_async_fifo_early_wr.v
.../../../../common/hdlmaker/v/pb_fifo_serializer4x1.v
.../../../../common/hdlmaker/v/pb_or_reduction.v
.../../../../common/hdlmaker/v/pb_packet_packer.v
.../../../../cores/pcs_layer/transmitter/v/pcs_tx_decode.v
.../../../../cores/pcs_layer/transmitter/v/pcs_tx_datapath_wide.v
.../../../../cores/pcs_layer/transmitter/v/aqdr_pcs_tx_lane.v
.../../../../cores/pcs_layer/transmitter/v/pcs_tx_ctrl.v
.../../../../cores/pcs_layer/transmitter/v/pcs_tx_input_ctrl.v
.../../../../common/hdlmaker/v/clk_1000mhz.v
.../../../../testbench/qdr_link_layer/ctrl_tb/v/ctrl_tb.v
.../../../../common/hdlmaker/v/delayline.v
.../../../../common/hdlmaker/v/glbl.v
.../../../../testbench/qdr_link_layer/ib_tb/v/ib_tb.v
.../../../../testbench/qdr_link_layer/ib_tb/v/ib_busphymon.v
.../../../../testbench/qdr_link_layer/ib_tb/v/ib_tsmon.v
.../../../../testbench/qdr_link_layer/ib_tb/v/ib_tsmonall.v
.../../../../testbench/qdr_link_layer/ib_tb/v/ib_clkdivider.v
.../../../../testbench/qdr_link_layer/ib_tb/v/ib_rxbfm.v
.../../../../testbench/qdr_link_layer/ib_tb/v/ib_txbfm.v
.../../../../testbench/qdr_link_layer/par_tb/v/par_tb.v
.../../../../testbench/qdr_link_layer/par_tb/v/par_rxbfm.v
.../../../../testbench/qdr_link_layer/par_tb/v/par_txbfm.v
.../../../../common/hdlmaker/v/pb_buffer.v
.../../../../common/hdlmaker/v/pb_dreg.v
.../../../../common/hdlmaker/v/pb_mux2x1.v
.../../../../common/hdlmaker/v/pb_mux4x1.v
.../../../../common/hdlmaker/v/pb_rmux2x1.v
.../../../../testbench/qdr_link_layer/ibtb_top/v/status_tb.v
.../../../../testbench/aqdr_link_layer/ibtb_top/v/tb_parameters.v
.../../../../testbench/qdr_link_layer/ib_tb/v/ib_rxsm.v
.../../../../testbench/qdr_link_layer/ib_tb/v/ib_phymon.v
.../../../../testbench/qdr_link_layer/ib_tb/v/packet_mon.v
.../../../../testbench/qdr_link_layer/ib_tb/v/ib_scheduler.v
.../../../../testbench/qdr_link_layer/ib_tb/v/ib_lphygen.v
.../../../../testbench/qdr_link_layer/ib_tb/v/ib_phygen.v
.../../../../testbench/qdr_link_layer/ib_tb/v/ib_linkscheduler.v
.../../../../testbench/qdr_link_layer/ib_tb/v/ib_traffic_scheduler.v
.../../../../testbench/qdr_link_layer/ib_tb/v/ib_txlanemux.v
.../../../../testbench/qdr_link_layer/ib_tb/v/ib_linkgen.v
.../../../../testbench/qdr_link_layer/ib_tb/v/ib_fcgen.v
.../../../../testbench/qdr_link_layer/ib_tb/v/packet_gen.v
.../../../../testbench/qdr_link_layer/ib_tb/v/lts_timer.v
.../../../../testbench/qdr_link_layer/ib_tb/v/ib_lts.v
.../../../../testbench/qdr_link_layer/ib_tb/v/ib_idlemon.v
.../../../../testbench/qdr_link_layer/ib_tb/v/ib_idlemon1.v
.../../../../testbench/qdr_link_layer/ib_tb/v/ib_idlegen.v
.../../../../testbench/qdr_link_layer/par_tb/v/par_scheduler.v
.../../../../testbench/qdr_link_layer/par_tb/v/par_traffic_scheduler.v
.../../../../testbench/qdr_link_layer/par_tb/v/par_txlanemux.v
.../../../../testbench/qdr_link_layer/par_tb/v/par_gen.v
.../../../../testbench/qdr_link_layer/ib_tb/v/ib_rxtbmux.v
.../../../../testbench/qdr_link_layer/ibtb_top/v/tcstat.v
+incdir+../../fpga_qdr/in

 

[Nico Coesel]

General Schvantzkoph <schvantzkoph@yahoo.com> wrote:

On Fri, 17 Sep 2010 14:04:42 -0700, rickman wrote:

On Sep 17, 11:19 am, General Schvantzkoph <schvantzk...@yahoo.com
wrote:
On Fri, 17 Sep 2010 07:20:41 -0700, rickman wrote:
On Sep 16, 8:40 pm, General Schvantzkoph <schvantzk...@yahoo.com
wrote:
On Thu, 16 Sep 2010 17:25:26 -0700, OutputLogic wrote:
Hi,

It'd be very convenient to post the manual in PDF or HTML format
online instead of requiring tool installation.

Thanks,
Evgeni

The manual is online. I admit that it's pretty mediocre, one of
these days I'll take the time to rewrite it.

http://www.polybus.com/hdlmaker/users_guide/id20.htm

http://www.polybus.com/hdlmaker/users_guide/id18.htm

Rather than make me read a mediocre manual, can you briefly describe
this software? What are the inputs to allow HDL to be generated?

Rick

HDLmaker sources are .top files which instantiate components and
contains directives for various tools and the .pin file which specify
ports as well as pin numbers, logic levels, io sets and resets, io
registering, and timing constraints. HDLmaker has a C like language
which allows you to calculate signal names, parameter values,
conditional operations and loops. The output of HDLmaker is either
Verilog or VHDL (depending on a switch). It has extensive support for
Xilinx and Altera tools as well as Synplify. It generates Make files
for Modelsim/Questa and filelists for NC and VCS. It generates UCF and
SDC constraint files, Quartus Projects, XST scripts. It also has
support for Xilinx floorplanning (you can generate floor plans using
it's C like language.

Where ever possible it uses common directives that are portable across
tools, for example the #clock command defines clocks, it generates the
appropriate constraints and directives for Xilinx, Altera, Synplify and
Precision. In addition to generic directives there are directives that
are specific to a tool like XST or Quartus. A design that's written in
HDLmaker is easily portable between tools and technologies and even
languages.

One of it's main features is that it automatically connects ports as
long as the port names are the same, i.e. port foo on modules X and Y
will be connected without having to specify it in the code. If you want
to connect a port to a different signal or bus then you use the connect
statement. Signal names and numbers can be calculated if you want,
HDlmaker does both integer and string arithmetic (for example "foo_a" +
2 becomes foo_c in the generated code, concatenations and integer and
string variables are also supported).

There are a number of examples on the web,

http://www.polybus.com/hdlmaker/users_guide/id25.htm

I think I'll add a few more examples in the next few weeks which
illustrate some of HDLmakers newer features.

So let me make sure I understand. HDLmaker allows us to program in its
own special language that is C like and largely structural rather than
programming in HDL both structurally specifying logic and/or inferring
logic.

What is better about this than coding in HDL? I don't get why you are
touting how your tool works with all brands. HDL by design is vendor
and device and in fact, technology independent. Most of what you list
above is not anything HDL doesn't do or that I would need to do.

Am I missing the point?

Rick

When I started writing HDLmaker in the early 90's Verilog didn't have any
generate capabilities and even today it's much less capable then HDLmaker.
In addition to generating code HDLmaker does the following automatically,

1) It generates project files, scripts, make files and constraint files for lots of different
tools. Once a design is in HDLmaker you can move from one tool to another
in seconds.

2) It builds the structure with minimum coding. In the most extreme case
where all of the ports on the leaf modules have corresponding names all
you have to do is list the components, for example,

#insert "foo.v";

#insert "bar.v";

#insert "more.top";

3) You can parametrize a design

#for(i=0;i<num_lanes;i++)
{
#assign vl = "_a" + i;
#assign lane = "lane_a" + i;
#assign credit = "credit_level" $ vl;

#insert "ib_link_ctrl_fctrl_lane.v",name = "fctrl_lane_",
#parameter VIRTUAL_LANE = i,
connect IB_CREDIT_LEVEL[12:0] = #credit[12:0],
connect IB_FLOW_CTRL_TIMEOUT = IB_FLOW_CTRL_TIMEOUT[#i],
connect IB_STAT_RX_ABR_ERR = rx_abr_err[#i],
connect IB_TX_CREDIT_AVAIL = IB_TX_CREDIT_AVAIL[#i],
connect IB_TX_CREDIT_OK = IB_TX_CREDIT_OK[#i],
connect flow_ctrl_violation = flow_ctrl_violation[#i],
connect high_priority_request = high_priority_request[#i],
connect lane[3:0] = #lane[3:0],
connect lane_operational = lane_operational[#i],
connect link_packet_ready = link_packet_ready,
connect link_packet_valid = link_packet_valid,
connect link_packet_vl[3:0] = link_packet_vl[3:0],
connect rx_abr[31:0] = "rx_abr" $ vl[31:0],
connect nxt_flow_ctrl_packet[31:0] = "nxt_flow_ctrl_packet" $ vl[31:0],
connect shadow_credit_near_empty = shadow_credit_near_empty[#i];
}

4) It's really easy to create your entire structure up front. All you have to do
is define the pin files and the top files for each level. HDLmaker tells you if
there are any undriven inputs or outputs or bus conflicts.

Here of a pin file. HDLmaker generates the ports of a module from this, including
the comments.

This seems to me like an extension to Verilog. VHDL already has the
features you describe.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

 

[Brad Smallridge]

Designing across language barriers sounds good.
Perhaps you should give us a simpler example.
What does a D Flipflop look like in your language.
What does the Verilog and VHDL look like after
it compiles(?).

"General Schvantzkoph" <schvantzkoph@yahoo.com> wrote in message
news:8fiiupF4btU3@mid.individual.net...

On Fri, 17 Sep 2010 14:04:42 -0700, rickman wrote:

On Sep 17, 11:19 am, General Schvantzkoph <schvantzk...@yahoo.com
wrote:
On Fri, 17 Sep 2010 07:20:41 -0700, rickman wrote:
On Sep 16, 8:40 pm, General Schvantzkoph <schvantzk...@yahoo.com
wrote:
On Thu, 16 Sep 2010 17:25:26 -0700, OutputLogic wrote:
Hi,

It'd be very convenient to post the manual in PDF or HTML format
online instead of requiring tool installation.

Thanks,
Evgeni

The manual is online. I admit that it's pretty mediocre, one of
these days I'll take the time to rewrite it.

http://www.polybus.com/hdlmaker/users_guide/id20.htm

http://www.polybus.com/hdlmaker/users_guide/id18.htm

Rather than make me read a mediocre manual, can you briefly describe
this software? What are the inputs to allow HDL to be generated?

Rick

HDLmaker sources are .top files which instantiate components and
contains directives for various tools and the .pin file which specify
ports as well as pin numbers, logic levels, io sets and resets, io
registering, and timing constraints. HDLmaker has a C like language
which allows you to calculate signal names, parameter values,
conditional operations and loops. The output of HDLmaker is either
Verilog or VHDL (depending on a switch). It has extensive support for
Xilinx and Altera tools as well as Synplify. It generates Make files
for Modelsim/Questa and filelists for NC and VCS. It generates UCF and
SDC constraint files, Quartus Projects, XST scripts. It also has
support for Xilinx floorplanning (you can generate floor plans using
it's C like language.

Where ever possible it uses common directives that are portable across
tools, for example the #clock command defines clocks, it generates the
appropriate constraints and directives for Xilinx, Altera, Synplify and
Precision. In addition to generic directives there are directives that
are specific to a tool like XST or Quartus. A design that's written in
HDLmaker is easily portable between tools and technologies and even
languages.

One of it's main features is that it automatically connects ports as
long as the port names are the same, i.e. port foo on modules X and Y
will be connected without having to specify it in the code. If you want
to connect a port to a different signal or bus then you use the connect
statement. Signal names and numbers can be calculated if you want,
HDlmaker does both integer and string arithmetic (for example "foo_a" +
2 becomes foo_c in the generated code, concatenations and integer and
string variables are also supported).

There are a number of examples on the web,

http://www.polybus.com/hdlmaker/users_guide/id25.htm

I think I'll add a few more examples in the next few weeks which
illustrate some of HDLmakers newer features.

So let me make sure I understand. HDLmaker allows us to program in its
own special language that is C like and largely structural rather than
programming in HDL both structurally specifying logic and/or inferring
logic.

What is better about this than coding in HDL? I don't get why you are
touting how your tool works with all brands. HDL by design is vendor
and device and in fact, technology independent. Most of what you list
above is not anything HDL doesn't do or that I would need to do.

Am I missing the point?

Rick

When I started writing HDLmaker in the early 90's Verilog didn't have any
generate capabilities and even today it's much less capable then HDLmaker.
In addition to generating code HDLmaker does the following automatically,

1) It generates project files, scripts, make files and constraint files
for lots of different
tools. Once a design is in HDLmaker you can move from one tool to another
in seconds.

2) It builds the structure with minimum coding. In the most extreme case
where all of the ports on the leaf modules have corresponding names all
you have to do is list the components, for example,

#insert "foo.v";

#insert "bar.v";

#insert "more.top";

3) You can parametrize a design

#for(i=0;i<num_lanes;i++)
{
#assign vl = "_a" + i;
#assign lane = "lane_a" + i;
#assign credit = "credit_level" $ vl;

#insert "ib_link_ctrl_fctrl_lane.v",name = "fctrl_lane_",
#parameter VIRTUAL_LANE = i,
connect IB_CREDIT_LEVEL[12:0] = #credit[12:0],
connect IB_FLOW_CTRL_TIMEOUT = IB_FLOW_CTRL_TIMEOUT[#i],
connect IB_STAT_RX_ABR_ERR = rx_abr_err[#i],
connect IB_TX_CREDIT_AVAIL = IB_TX_CREDIT_AVAIL[#i],
connect IB_TX_CREDIT_OK = IB_TX_CREDIT_OK[#i],
connect flow_ctrl_violation = flow_ctrl_violation[#i],
connect high_priority_request = high_priority_request[#i],
connect lane[3:0] = #lane[3:0],
connect lane_operational = lane_operational[#i],
connect link_packet_ready = link_packet_ready,
connect link_packet_valid = link_packet_valid,
connect link_packet_vl[3:0] = link_packet_vl[3:0],
connect rx_abr[31:0] = "rx_abr" $ vl[31:0],
connect nxt_flow_ctrl_packet[31:0] = "nxt_flow_ctrl_packet" $ vl[31:0],
connect shadow_credit_near_empty = shadow_credit_near_empty[#i];
}

4) It's really easy to create your entire structure up front. All you have
to do
is define the pin files and the top files for each level. HDLmaker tells
you if
there are any undriven inputs or outputs or bus conflicts.

Here of a pin file. HDLmaker generates the ports of a module from this,
including
the comments.

#nopadring
#pins
IB_LINK_STATE[2:0] type = in, comment = "Link State, see Vol 1, section
7.2 of the IBA spec
0 LINK_DOWN
1 LINK_INIT
2 LINK_ARM
3 LINK_ACTIVE
4 LINK_ACT_DEFER";

DLANE_OFFSET[2:0] type = in,comment = "Base Virtual Lane";
IB_BUFFER_SIZE[11:0] type = in, comment = "Buffer space in 64 byte
credits";
IB_BUFFER_SIZE_REQ[3:0] type = out,comment = "VL of the free space
request";
IB_BUFFER_SIZE_REQ_VALID type = out,comment = "Request free space in VL
buffer";
IB_BUFFER_SIZE_VALID type = in,comment = "Buffer size valud is valid";
IB_BUFFER_SIZE_VL[3:0] type = in,comment = "VL of buffer space value";
#endpins

5) It generates both Verilog and VHDL code so you can reuse code in both
environment.

6) For the top level of an FPGA you can specify all aspects of the pins in
a single file.

#uselibrary
#pins
REF_CLK type = in,logic = PASS,iostandard="1.4-V PCML",input_term =
"OCT_100_ohms",comment = "625MHz reference 312",pin = [AL38];

SD_TX[3:0] type = out,logic = "PASS",comment = "SerDes serial
out",iostandard="1.4-V PCML",output_term="OCT 100
OHMS",pin=[AD36,AB36,T36,P36];
SD_RX[3:0] type = in,logic = "PASS",comment = "SerDes Serial
in",iostandard="1.4-V PCML",input_term="OCT 100
OHMS",pin=[AE38,AC38,U38,R38];
PARAM_SEL[7:0] type = in,comment = "LSBs of the LID, from switches",pin=
[AM26,AN26,AP26,AN27,AP27,AT27,AU27,AW27];
gblreset_l type = in,comment = "Global Async reset",pin=AW18;
#endpins

This will generate not only the Verilog or VHDL for the top level module
and the pad ring module but it will also generate the constraint files
(ucf for Xilinx, the Quartus project file for Altera).

7) Making changes are really easy, mostly all you have to do is make the
changes in the leaf modules,
the structural code is generated by HDLmaker.

8) Coping tool directives from one project to another is easier because
you just have to copy a few lines from a text file. Here are the Quartus
directives from one of my projects,


#beneficial_skew_opt 1;
#combo_logic_for_area 1;
#equiv_logic_removal 0;
#fitter_aggressive_mode "automatically";
#gen_mif 1;
#hold_timing_min_tpd 1;
#mux_restructure 1;
#placement_effort 4;
#register_balancing "yes";
#register_duplication 1;
#remove_duplicate_logic 0;
#rom_recognition 1;
#router_effort 3;
#smart_recompile 0;
#verilog2001 "yes";
#timequest 1;
#signal_tap "demo.stp";
#derive_clocks;

Here is the Quartus project that HDLmaker generated for this design,

# Quartus project file, Generated by HDLmaker Rev 9.3.7
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.0"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "Sept 17, 2010"
set_global_assignment -name LAST_QUARTUS_VERSION "10.0"
set_global_assignment -name VERILOG_FILE
../../../common/hdlmaker/v/fpga_defs.vh
set_global_assignment -name VERILOG_FILE
../../../reference_designs/aqdr_link_layer/altera/s4gx/v/s4gt_demo_625.v
set_global_assignment -name VERILOG_FILE
../../../unit_tests/aqdr_link_layer/common/v/aqdr_traffic_gen.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/fpga/s4gx/v/s4gt_aqdr_link_625.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/top_level/v/aqdr_pcs_link_fpga_10b.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/top_level/v/aqdr_ib_link_layer.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_control.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_clk_ctrl.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/control/init_and_training/v/aqdr_ib_link_ctrl_init_training.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/control/link_state/v/aqdr_ib_link_ctrl_state_machine.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/flow_control/vlanes_8/v/aqdr_ib_link_multilane_fctrl.v
set_global_assignment -name VERILOG_FILE ../../../common/crc/v/CRC16_D32.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/flow_control/common/v/aqdr_ib_link_ctrl_fctrl_common.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/flow_control/common/v/aqdr_ib_link_ctrl_fctrl_lane.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/receiver/common/v/aqdr_ib_link_receiver.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/receiver/crc/v/aqdr_ib_link_rx_crc.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/crc/v/aqdr_ib_rx_icrc_generator.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/crc/v/aqdr_ib_rx_icrc_mask.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/crc/v/aqdr_rx_crc32x128.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/crc/v/aqdr_rx_crc16x128.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_datapath.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_assembler.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_datapipe.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_stage.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/receiver/status/v/aqdr_ib_link_rx_status.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/transmitter/common/v/aqdr_ib_link_transmitter.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/transmitter/crc/v/aqdr_ib_link_xmit_crc_gen.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/crc/v/aqdr_ib_icrc_generator_128.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/crc/v/aqdr_ib_icrc_mask.v
set_global_assignment -name VERILOG_FILE
../../../common/crc/v/pb_tx_crc32x128.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/crc/v/aqdr_ib_vcrc_generator_128.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/crc/v/aqdr_ib_vcrc_ctrl.v
set_global_assignment -name VERILOG_FILE
../../../common/crc/v/pb_crc16x128.v
set_global_assignment -name VERILOG_FILE
../../../common/crc/v/pb_crc16x32.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_xmit_dpath.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_tx_mux.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_xmit_ctrl.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_xmit_status.v
set_global_assignment -name VERILOG_FILE
../../../common/hdlmaker/v/dregce_sr.v
set_global_assignment -name VERILOG_FILE
../../../cores/pcs_layer/top_level/v/aqdr_pcs_wide_10b.v
set_global_assignment -name VERILOG_FILE
../../../cores/pcs_layer/top_level/v/aqdr_pcs_wide_8b.v
set_global_assignment -name VERILOG_FILE
../../../cores/pcs_layer/top_level/v/aqdr_pcs_reset.v
set_global_assignment -name VERILOG_FILE
../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_wide.v
set_global_assignment -name VERILOG_FILE
../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_align_wide.v
set_global_assignment -name VERILOG_FILE
../../../cores/pcs_layer/receiver/v/aqdr_pcs_alignment_buffer.v
set_global_assignment -name VERILOG_FILE
../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_ctrl.v
set_global_assignment -name VERILOG_FILE
../../../common/hdlmaker/v/pb_mux2x1.v
set_global_assignment -name VERILOG_FILE
../../../common/hdlmaker/v/pb_offset_reg.v
set_global_assignment -name VERILOG_FILE
../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_swap_wide.v
set_global_assignment -name VERILOG_FILE
../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_swap_ctrl.v
set_global_assignment -name VERILOG_FILE
../../../common/hdlmaker/v/pb_regmux2x1.v
set_global_assignment -name VERILOG_FILE
../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_training_wide.v
set_global_assignment -name VERILOG_FILE
../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_training_ctrl.v
set_global_assignment -name VERILOG_FILE
../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_training_lane_wide.v
set_global_assignment -name VERILOG_FILE
../../../common/hdlmaker/v/pb_fifo_deserializer1x4.v
set_global_assignment -name VERILOG_FILE
../../../cores/pcs_layer/receiver/v/pcs_rx_loopback.v
set_global_assignment -name VERILOG_FILE
../../../common/hdlmaker/v/pb_async_fifo.v
set_global_assignment -name VERILOG_FILE
../../../common/hdlmaker/v/pb_cmux2x1.v
set_global_assignment -name VERILOG_FILE
../../../common/hdlmaker/v/pb_match_ab.v
set_global_assignment -name VERILOG_FILE
../../../cores/pcs_layer/receiver/v/pcs_rx_lpbk_ctrl.v
set_global_assignment -name VERILOG_FILE
../../../common/hdlmaker/v/buffer.v
set_global_assignment -name VERILOG_FILE
../../../cores/pcs_layer/transmitter/v/pcs_tx_wide.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/pcs/v/aqdr_pcs_tx_idle_gen_wide.v
set_global_assignment -name VERILOG_FILE
../../../cores/aqdr_link_layer/pcs/v/aqdr_link_idle_gen.v
set_global_assignment -name VERILOG_FILE
../../../cores/pcs_layer/transmitter/v/aqdr_pcs_tx_swap.v
set_global_assignment -name VERILOG_FILE
../../../common/hdlmaker/v/pb_mux4x1.v
set_global_assignment -name VERILOG_FILE
../../../common/hdlmaker/v/pb_mux8x1.v
set_global_assignment -name VERILOG_FILE
../../../cores/pcs_layer/transmitter/v/pcs_tx_buffer_wide.v
set_global_assignment -name VERILOG_FILE
../../../common/hdlmaker/v/pb_async_fifo_early_wr.v
set_global_assignment -name VERILOG_FILE
../../../common/hdlmaker/v/pb_fifo_serializer4x1.v
set_global_assignment -name VERILOG_FILE
../../../common/hdlmaker/v/pb_or_reduction.v
set_global_assignment -name VERILOG_FILE
../../../common/hdlmaker/v/pb_packet_packer.v
set_global_assignment -name VERILOG_FILE
../../../cores/pcs_layer/transmitter/v/pcs_tx_decode.v
set_global_assignment -name VERILOG_FILE
../../../cores/pcs_layer/transmitter/v/pcs_tx_datapath_wide.v
set_global_assignment -name VERILOG_FILE
../../../cores/pcs_layer/transmitter/v/aqdr_pcs_tx_lane.v
set_global_assignment -name VERILOG_FILE
../../../cores/pcs_layer/transmitter/v/pcs_tx_ctrl.v
set_global_assignment -name VERILOG_FILE
../../../cores/pcs_layer/transmitter/v/pcs_tx_input_ctrl.v
set_global_assignment -name VERILOG_FILE
../../../common/hdlmaker/v/pb_base_x_decode_wide_4x.v
set_global_assignment -name VERILOG_FILE
../../../common/hdlmaker/v/pb_base_x_decode_wide.v
set_global_assignment -name VERILOG_FILE
../../../common/hdlmaker/v/pb_comma_align.v
set_global_assignment -name VERILOG_FILE
../../../common/hdlmaker/v/pb_decode_8b10b.v
set_global_assignment -name VERILOG_FILE
../../../common/hdlmaker/v/pb_decode_8b10b_ctrl.v
set_global_assignment -name VERILOG_FILE
../../../common/hdlmaker/v/pb_base_x_encode_wide_4x.v
set_global_assignment -name VERILOG_FILE
../../../common/hdlmaker/v/pb_base_x_encode_wide.v
set_global_assignment -name VERILOG_FILE
../../../common/hdlmaker/v/pb_encode_8b10b.v
set_global_assignment -name VERILOG_FILE
../../../common/hdlmaker/v/pb_igate.v
set_global_assignment -name VERILOG_FILE
../../../common/s4gx/v/s4gt_sd_qdr_625.v
set_global_assignment -name VERILOG_FILE
../../../common/hdlmaker/v/pb_dreg.v
set_global_assignment -name VERILOG_FILE
../../../common/s4gx/v/s4gt_625_rom.v
set_global_assignment -name VERILOG_FILE
../../../common/s4gx/v/s4gt_wide_qdr_625.v
set_global_assignment -name VERILOG_FILE
../../../common/s4gx/v/s4gx_config_ctrl_4x.v
set_global_assignment -name VERILOG_FILE
../../../common/s4gx/v/s4gx_reconfig.v
set_global_assignment -name VERILOG_FILE
../../../common/s4gx/v/s4gt_clk_260_625_ref.v
set_global_assignment -name VERILOG_FILE
../../../reference_designs/aqdr_link_layer/altera/s4gx/v/s4gt_demo_625_pads.v
set_global_assignment -name VERILOG_FILE
../../../common/hdlmaker/v/PB_IBUF.v
set_global_assignment -name VERILOG_FILE
../../../common/hdlmaker/v/PB_OBUF.v

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name SAFE_STATE_MACHINE ON
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION
AUTOMATICALLY
set_global_assignment -name REMOVE_DUPLICATE_LOGIC OFF
set_global_assignment -name PARALLEL_SYNTHESIS ON
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name AUTO_ROM_RECOGNITION ON
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION
ON
set_global_assignment -name STATE_MACHINE_PROCESSING AUTO
set_global_assignment -name MUX_RESTRUCTURE ON
set_global_assignment -name AUTO_RESOURCE_SHARING ON
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 1517
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 2
set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001
set_global_assignment -name FAMILY "STRATIX IV"
set_global_assignment -name TOP_LEVEL_ENTITY s4gt_demo_625
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF

# Fitter Assignments
# ==================
set_global_assignment -name OPTIMIZE_FAST_CORNER_TIMING ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_instance_assignment -name MAX_FANOUT "32" -to *
set_global_assignment -name ROUTER_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name DEVICE EP4S100G2F40i2
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name OPTIMIZE_TIMING "EXTRA EFFORT"
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION ON
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 3
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 4
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_GATE_RETIME ON

# -------------------
# start CLOCK(REF_CLK)

set_global_assignment -name FMAX_REQUIREMENT "630 MHz" -section_id REF_CLK
set_global_assignment -name DUTY_CYCLE 50 -section_id REF_CLK

# end CLOCK(REF_CLK)
# -----------------
set_global_assignment -name ENABLE_DRC_SETTINGS ON
set_global_assignment -name ENABLE_CLOCK_LATENCY ON
set_global_assignment -name SMART_RECOMPILE OFF
set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS ON
set_global_assignment -name IGNORE_LCELL_BUFFERS ON
set_global_assignment -name
PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS OFF
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "NORMAL
COMPILATION"
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
set_global_assignment -name SDC_FILE ../constraints/s4gt_demo_625.sdc
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name SDC_FILE ../constraints/s4gt_demo_625.sdc
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF ON
set_global_assignment -name SAVE_DISK_SPACE ON
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS OFF
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD
PATHS"
set_global_assignment -name SIGNALTAP_FILE
../../../reference_designs/aqdr_link_layer/altera/s4gx/constraints/demo.stp
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name USE_SIGNALTAP_FILE
../../../reference_designs/aqdr_link_layer/altera/s4gx/constraints/demo.stp
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name EDA_SIMULATION_TOOL "NC-Verilog (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "100 ps" -section_id
eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG
HDL" -section_id eda_simulation
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY ON -section_id
eda_simulation
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS ON -section_id
eda_simulation
set_location_assignment PIN_AW27 -to PARAM_SEL_pin[0]
set_location_assignment PIN_AU27 -to PARAM_SEL_pin[1]
set_location_assignment PIN_AT27 -to PARAM_SEL_pin[2]
set_location_assignment PIN_AP27 -to PARAM_SEL_pin[3]
set_location_assignment PIN_AN27 -to PARAM_SEL_pin[4]
set_location_assignment PIN_AP26 -to PARAM_SEL_pin[5]
set_location_assignment PIN_AN26 -to PARAM_SEL_pin[6]
set_location_assignment PIN_AM26 -to PARAM_SEL_pin[7]
set_location_assignment PIN_AL38 -to REF_CLK
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to REF_CLK
set_instance_assignment -name INPUT_TERMINATION "OCT_100_OHMS" -to REF_CLK
set_location_assignment PIN_R38 -to SD_RX[0]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_RX[0]
set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to
SD_RX[0]
set_location_assignment PIN_U38 -to SD_RX[1]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_RX[1]
set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to
SD_RX[1]
set_location_assignment PIN_AC38 -to SD_RX[2]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_RX[2]
set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to
SD_RX[2]
set_location_assignment PIN_AE38 -to SD_RX[3]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_RX[3]
set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to
SD_RX[3]
set_location_assignment PIN_P36 -to SD_TX[0]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_TX[0]
set_instance_assignment -name OUTPUT_TERMINATION "OCT 100 OHMS" -to
SD_TX[0]
set_location_assignment PIN_T36 -to SD_TX[1]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_TX[1]
set_instance_assignment -name OUTPUT_TERMINATION "OCT 100 OHMS" -to
SD_TX[1]
set_location_assignment PIN_AB36 -to SD_TX[2]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_TX[2]
set_instance_assignment -name OUTPUT_TERMINATION "OCT 100 OHMS" -to
SD_TX[2]
set_location_assignment PIN_AD36 -to SD_TX[3]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_TX[3]
set_instance_assignment -name OUTPUT_TERMINATION "OCT 100 OHMS" -to
SD_TX[3]
set_location_assignment PIN_AW18 -to gblreset_l_pin
set_location_assignment PIN_AN30 -to led_its_alive_pin
set_location_assignment PIN_AV29 -to led_link_active_pin
set_location_assignment PIN_AT29 -to led_link_ddr_pin
set_location_assignment PIN_AU29 -to led_link_qdr_pin
set_location_assignment PIN_AP30 -to led_link_rx_error_pin
set_location_assignment PIN_AW29 -to led_link_up_pin
set_location_assignment PIN_AW30 -to led_loopback_pin
set_location_assignment PIN_AT30 -to led_pass_pin

###############################################################
Here is the Modelsim Make file that HDLmaker generated for this project


VLOG_ARG_FILES = \
v/fpga.defs \
v/idle.defs



VLOG_ARGS = \
-f v/fpga.defs \
-f v/idle.defs


MODEL_OBJS = \
work/tcstat \
work/ib_rxtbmux \
work/par_gen \
work/par_txlanemux \
work/par_traffic_scheduler \
work/par_scheduler \
work/ib_idlegen \
work/ib_idlemon1 \
work/ib_idlemon \
work/ib_lts \
work/lts_timer \
work/packet_gen \
work/ib_fcgen \
work/ib_linkgen \
work/ib_txlanemux \
work/ib_traffic_scheduler \
work/ib_linkscheduler \
work/ib_phygen \
work/ib_lphygen \
work/ib_scheduler \
work/packet_mon \
work/ib_phymon \
work/ib_rxsm \
work/tb_parameters \
work/status_tb \
work/pb_rmux2x1 \
work/pb_mux4x1 \
work/pb_mux2x1 \
work/pb_dreg \
work/pb_buffer \
work/par_txbfm \
work/par_rxbfm \
work/par_tb \
work/ib_txbfm \
work/ib_rxbfm \
work/ib_clkdivider \
work/ib_tsmonall \
work/ib_tsmon \
work/ib_busphymon \
work/ib_tb \
work/glbl \
work/delayline \
work/ctrl_tb \
work/clk_1000mhz \
work/pcs_tx_input_ctrl \
work/pcs_tx_ctrl \
work/aqdr_pcs_tx_lane \
work/pcs_tx_datapath_wide \
work/pcs_tx_decode \
work/pb_packet_packer \
work/pb_or_reduction \
work/pb_fifo_serializer4x1 \
work/pb_async_fifo_early_wr \
work/pcs_tx_buffer_wide \
work/pb_mux8x1 \
work/aqdr_pcs_tx_swap \
work/aqdr_link_idle_gen \
work/aqdr_pcs_tx_idle_gen_wide \
work/pcs_tx_wide \
work/buffer \
work/pcs_rx_lpbk_ctrl \
work/pb_match_ab \
work/pb_cmux2x1 \
work/pb_async_fifo \
work/pcs_rx_loopback \
work/pb_fifo_deserializer1x4 \
work/aqdr_pcs_rx_training_lane_wide \
work/aqdr_pcs_rx_training_ctrl \
work/aqdr_pcs_rx_training_wide \
work/pb_regmux2x1 \
work/aqdr_pcs_rx_swap_ctrl \
work/aqdr_pcs_rx_swap_wide \
work/pb_offset_reg \
work/aqdr_pcs_rx_ctrl \
work/aqdr_pcs_alignment_buffer \
work/aqdr_pcs_rx_align_wide \
work/aqdr_pcs_rx_wide \
work/aqdr_pcs_reset \
work/aqdr_pcs_wide_8b \
work/dregce_sr \
work/aqdr_ib_link_xmit_status \
work/aqdr_ib_link_xmit_ctrl \
work/aqdr_ib_link_tx_mux \
work/aqdr_ib_link_xmit_dpath \
work/pb_crc16x32 \
work/pb_crc16x128 \
work/aqdr_ib_vcrc_ctrl \
work/aqdr_ib_vcrc_generator_128 \
work/pb_tx_crc32x128 \
work/aqdr_ib_icrc_mask \
work/aqdr_ib_icrc_generator_128 \
work/aqdr_ib_link_xmit_crc_gen \
work/aqdr_ib_link_transmitter \
work/aqdr_ib_link_rx_status \
work/aqdr_ib_link_rx_stage \
work/aqdr_ib_link_rx_datapipe \
work/aqdr_ib_link_rx_assembler \
work/aqdr_ib_link_rx_datapath \
work/aqdr_rx_crc16x128 \
work/aqdr_rx_crc32x128 \
work/aqdr_ib_rx_icrc_mask \
work/aqdr_ib_rx_icrc_generator \
work/aqdr_ib_link_rx_crc \
work/aqdr_ib_link_receiver \
work/aqdr_ib_link_ctrl_fctrl_lane \
work/aqdr_ib_link_ctrl_fctrl_common \
work/CRC16_D32 \
work/aqdr_ib_link_multilane_fctrl \
work/aqdr_ib_link_ctrl_state_machine \
work/aqdr_ib_link_ctrl_init_training \
work/aqdr_ib_link_clk_ctrl \
work/aqdr_ib_link_control \
work/aqdr_ib_link_layer \
work/aqdr_pcs_link_fpga_8b \
work/fpga_defs \
work/ibtb_top \
work/idle_defs \
work


all: $(MODEL_OBJS)


work:
vlib work


clean:
rm -Rf work
vlib work


work/idle_defs: ../../fpga_qdr/v/idle_defs.vh $(VLOG_ARG_FILES)
vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS)
../../fpga_qdr/v/idle_defs.vh
touch work/idle_defs

work/ibtb_top: ../../../../testbench/aqdr_link_layer/fpga_qdr/v/ibtb_top.v
$(VLOG_ARG_FILES)
vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS)
../../../../testbench/aqdr_link_layer/fpga_qdr/v/ibtb_top.v
touch work/ibtb_top

work/fpga_defs: ../../../../common/hdlmaker/v/fpga_defs.vh
$(VLOG_ARG_FILES)
vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS)
../../../../common/hdlmaker/v/fpga_defs.vh
touch work/fpga_defs

work/aqdr_pcs_link_fpga_8b:
../../../../cores/aqdr_link_layer/top_level/v/aqdr_pcs_link_fpga_8b.v
$(VLOG_ARG_FILES)
vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS)
../../../../cores/aqdr_link_layer/top_level/v/aqdr_pcs_link_fpga_8b.v
touch work/aqdr_pcs_link_fpga_8b

work/aqdr_ib_link_layer:
../../../../cores/aqdr_link_layer/top_level/v/aqdr_ib_link_layer.v
$(VLOG_ARG_FILES)
vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS)
../../../../cores/aqdr_link_layer/top_level/v/aqdr_ib_link_layer.v
touch work/aqdr_ib_link_layer

work/aqdr_ib_link_control:
../../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_control.v
$(VLOG_ARG_FILES)
vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS)
../../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_control.v
touch work/aqdr_ib_link_control

work/aqdr_ib_link_clk_ctrl:
../../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_clk_ctrl.v
$(VLOG_ARG_FILES)
vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS)
../../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_clk_ctrl.v
touch work/aqdr_ib_link_clk_ctrl

work/aqdr_ib_link_ctrl_init_training:
../../../../cores/aqdr_link_layer/control/init_and_training/v/aqdr_ib_link_ctrl_init_training.v
$(VLOG_ARG_FILES)
vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS)
../../../../cores/aqdr_link_layer/control/init_and_training/v/aqdr_ib_link_ctrl_init_training.v
touch work/aqdr_ib_link_ctrl_init_training

work/aqdr_ib_link_ctrl_state_machine:
../../../../cores/aqdr_link_layer/control/link_state/v/aqdr_ib_link_ctrl_state_machine.v
$(VLOG_ARG_FILES)
vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS)
../../../../cores/aqdr_link_layer/control/link_state/v/aqdr_ib_link_ctrl_state_machine.v
touch work/aqdr_ib_link_ctrl_state_machine

###########################################

Here is the file list that it generated for NCsim,

../../fpga_qdr/v/idle_defs.vh
../../../../testbench/aqdr_link_layer/fpga_qdr/v/ibtb_top.v
../../../../common/hdlmaker/v/fpga_defs.vh
../../../../cores/aqdr_link_layer/top_level/v/aqdr_pcs_link_fpga_8b.v
../../../../cores/aqdr_link_layer/top_level/v/aqdr_ib_link_layer.v
../../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_control.v
../../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_clk_ctrl.v
../../../../cores/aqdr_link_layer/control/init_and_training/v/aqdr_ib_link_ctrl_init_training.v
../../../../cores/aqdr_link_layer/control/link_state/v/aqdr_ib_link_ctrl_state_machine.v
../../../../cores/aqdr_link_layer/flow_control/vlanes_8/v/aqdr_ib_link_multilane_fctrl.v
../../../../common/crc/v/CRC16_D32.v
../../../../cores/aqdr_link_layer/flow_control/common/v/aqdr_ib_link_ctrl_fctrl_common.v
../../../../cores/aqdr_link_layer/flow_control/common/v/aqdr_ib_link_ctrl_fctrl_lane.v
../../../../cores/aqdr_link_layer/receiver/common/v/aqdr_ib_link_receiver.v
../../../../cores/aqdr_link_layer/receiver/crc/v/aqdr_ib_link_rx_crc.v
../../../../cores/aqdr_link_layer/crc/v/aqdr_ib_rx_icrc_generator.v
../../../../cores/aqdr_link_layer/crc/v/aqdr_ib_rx_icrc_mask.v
../../../../cores/aqdr_link_layer/crc/v/aqdr_rx_crc32x128.v
../../../../cores/aqdr_link_layer/crc/v/aqdr_rx_crc16x128.v
../../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_datapath.v
../../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_assembler.v
../../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_datapipe.v
../../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_stage.v
../../../../cores/aqdr_link_layer/receiver/status/v/aqdr_ib_link_rx_status.v
../../../../cores/aqdr_link_layer/transmitter/common/v/aqdr_ib_link_transmitter.v
../../../../cores/aqdr_link_layer/transmitter/crc/v/aqdr_ib_link_xmit_crc_gen.v
../../../../cores/aqdr_link_layer/crc/v/aqdr_ib_icrc_generator_128.v
../../../../cores/aqdr_link_layer/crc/v/aqdr_ib_icrc_mask.v
../../../../common/crc/v/pb_tx_crc32x128.v
../../../../cores/aqdr_link_layer/crc/v/aqdr_ib_vcrc_generator_128.v
../../../../cores/aqdr_link_layer/crc/v/aqdr_ib_vcrc_ctrl.v
../../../../common/crc/v/pb_crc16x128.v
../../../../common/crc/v/pb_crc16x32.v
../../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_xmit_dpath.v
../../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_tx_mux.v
../../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_xmit_ctrl.v
../../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_xmit_status.v
../../../../common/hdlmaker/v/dregce_sr.v
../../../../cores/pcs_layer/top_level/v/aqdr_pcs_wide_8b.v
../../../../cores/pcs_layer/top_level/v/aqdr_pcs_reset.v
../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_wide.v
../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_align_wide.v
../../../../cores/pcs_layer/receiver/v/aqdr_pcs_alignment_buffer.v
../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_ctrl.v
../../../../common/hdlmaker/v/pb_offset_reg.v
../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_swap_wide.v
../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_swap_ctrl.v
../../../../common/hdlmaker/v/pb_regmux2x1.v
../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_training_wide.v
../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_training_ctrl.v
../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_training_lane_wide.v
../../../../common/hdlmaker/v/pb_fifo_deserializer1x4.v
../../../../cores/pcs_layer/receiver/v/pcs_rx_loopback.v
../../../../common/hdlmaker/v/pb_async_fifo.v
../../../../common/hdlmaker/v/pb_cmux2x1.v
../../../../common/hdlmaker/v/pb_match_ab.v
../../../../cores/pcs_layer/receiver/v/pcs_rx_lpbk_ctrl.v
../../../../common/hdlmaker/v/buffer.v
../../../../cores/pcs_layer/transmitter/v/pcs_tx_wide.v
../../../../cores/aqdr_link_layer/pcs/v/aqdr_pcs_tx_idle_gen_wide.v
../../../../cores/aqdr_link_layer/pcs/v/aqdr_link_idle_gen.v
../../../../cores/pcs_layer/transmitter/v/aqdr_pcs_tx_swap.v
../../../../common/hdlmaker/v/pb_mux8x1.v
../../../../cores/pcs_layer/transmitter/v/pcs_tx_buffer_wide.v
../../../../common/hdlmaker/v/pb_async_fifo_early_wr.v
../../../../common/hdlmaker/v/pb_fifo_serializer4x1.v
../../../../common/hdlmaker/v/pb_or_reduction.v
../../../../common/hdlmaker/v/pb_packet_packer.v
../../../../cores/pcs_layer/transmitter/v/pcs_tx_decode.v
../../../../cores/pcs_layer/transmitter/v/pcs_tx_datapath_wide.v
../../../../cores/pcs_layer/transmitter/v/aqdr_pcs_tx_lane.v
../../../../cores/pcs_layer/transmitter/v/pcs_tx_ctrl.v
../../../../cores/pcs_layer/transmitter/v/pcs_tx_input_ctrl.v
../../../../common/hdlmaker/v/clk_1000mhz.v
../../../../testbench/qdr_link_layer/ctrl_tb/v/ctrl_tb.v
../../../../common/hdlmaker/v/delayline.v
../../../../common/hdlmaker/v/glbl.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_tb.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_busphymon.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_tsmon.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_tsmonall.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_clkdivider.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_rxbfm.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_txbfm.v
../../../../testbench/qdr_link_layer/par_tb/v/par_tb.v
../../../../testbench/qdr_link_layer/par_tb/v/par_rxbfm.v
../../../../testbench/qdr_link_layer/par_tb/v/par_txbfm.v
../../../../common/hdlmaker/v/pb_buffer.v
../../../../common/hdlmaker/v/pb_dreg.v
../../../../common/hdlmaker/v/pb_mux2x1.v
../../../../common/hdlmaker/v/pb_mux4x1.v
../../../../common/hdlmaker/v/pb_rmux2x1.v
../../../../testbench/qdr_link_layer/ibtb_top/v/status_tb.v
../../../../testbench/aqdr_link_layer/ibtb_top/v/tb_parameters.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_rxsm.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_phymon.v
../../../../testbench/qdr_link_layer/ib_tb/v/packet_mon.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_scheduler.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_lphygen.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_phygen.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_linkscheduler.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_traffic_scheduler.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_txlanemux.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_linkgen.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_fcgen.v
../../../../testbench/qdr_link_layer/ib_tb/v/packet_gen.v
../../../../testbench/qdr_link_layer/ib_tb/v/lts_timer.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_lts.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_idlemon.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_idlemon1.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_idlegen.v
../../../../testbench/qdr_link_layer/par_tb/v/par_scheduler.v
../../../../testbench/qdr_link_layer/par_tb/v/par_traffic_scheduler.v
../../../../testbench/qdr_link_layer/par_tb/v/par_txlanemux.v
../../../../testbench/qdr_link_layer/par_tb/v/par_gen.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_rxtbmux.v
../../../../testbench/qdr_link_layer/ibtb_top/v/tcstat.v
+incdir+../../fpga_qdr/in

 

[General Schvantzkoph]

On Sat, 18 Sep 2010 17:32:48 -0700, Brad Smallridge wrote:

Designing across language barriers sounds good. Perhaps you should give
us a simpler example. What does a D Flipflop look like in your language.
What does the Verilog and VHDL look like after it compiles(?).

HDLmaker builds structural code, you still have to write the leaf cells.
What it does is hook everything together for you. In addition it creates
the project, constraint, script and make files for all of the most common
tools. It has other capabilities also, for example it will convert the MIF
files that Quartus generates in to Verilog code.