new Lattice FPGAs vs Cyclone and SpartanIII

P

Paul Sereno

Guest
I am just wandering if any of you have take a look at the Lattice
FPGAs. I do like the DSP functions.
is out there any serious comparation against SpartanIII and Cyclone?

regards,

paul
 
What special did u find on it?? on the first glance it looks similar
to what altera is proving for year as DSP block

paul_sereno@hotmail.com (Paul Sereno) wrote in message news:<3d7510b4.0407021019.c3a5df5@posting.google.com>...
I am just wandering if any of you have take a look at the Lattice
FPGAs. I do like the DSP functions.
is out there any serious comparation against SpartanIII and Cyclone?

regards,

paul
 
IMHO, Altera's DSP block is only a multiplier. The MAC block Lattice
is proposing is much richer: reg, mult, pipeline reg, accu, reg. On
top of it, the IO cell has more regs than any other comparable
architecture.
Anyone tried to implement DDR333 on Cyclone or S3?

rgrds,

On 4 Jul 2004 23:42:00 -0700, digari@dacafe.com (digari) wrote:

What special did u find on it?? on the first glance it looks similar
to what altera is proving for year as DSP block

paul_sereno@hotmail.com (Paul Sereno) wrote in message news:<3d7510b4.0407021019.c3a5df5@posting.google.com>...
I am just wandering if any of you have take a look at the Lattice
FPGAs. I do like the DSP functions.
is out there any serious comparation against SpartanIII and Cyclone?

regards,

paul
 
Luc Braeckman <luc.braeckman@pandora.be> wrote in message news:<co4ie010ld9h69mmp8i09l86i5l0uhs13a@4ax.com>...
IMHO, Altera's DSP block is only a multiplier. The MAC block Lattice
is proposing is much richer: reg, mult, pipeline reg, accu, reg. On
top of it, the IO cell has more regs than any other comparable
architecture.
Please have a look at:
http://www.altera.com/products/devices/stratix/features/stx-dsp.html
and then see where Latice got thier ideas from. But you are correct
for the lowcost families Altera (CycloneII) and Xilinx (spartan-3) has
chosen Multipliers rather then DSP blocks. Put if you call Alteras DSP
block a mulitiplyer you have to say the same about Latice since there
are at least on the marketing slides I have seen identical.
YMHO
Fredrik
 
Fredrik,

I don't want to start a discussion about the chicken and the egg and..
You are right about Stratix, but Lattice has implemented them in a low
cost device, and there is the advantage. If you don't want to spend
lot's of $$ on features you're not going to use, this ECP-DSP family
is a very good alternative, and the performance ... well look for
yourselve and try a benchmark.
Luc
___
for On 5 Jul 2004 23:11:54 -0700, fredrik_he_lang@hotmail.com
(Fredrik) wrote:

Luc Braeckman <luc.braeckman@pandora.be> wrote in message news:<co4ie010ld9h69mmp8i09l86i5l0uhs13a@4ax.com>...
IMHO, Altera's DSP block is only a multiplier. The MAC block Lattice
is proposing is much richer: reg, mult, pipeline reg, accu, reg. On
top of it, the IO cell has more regs than any other comparable
architecture.
Please have a look at:
http://www.altera.com/products/devices/stratix/features/stx-dsp.html
and then see where Latice got thier ideas from. But you are correct
for the lowcost families Altera (CycloneII) and Xilinx (spartan-3) has
chosen Multipliers rather then DSP blocks. Put if you call Alteras DSP
block a mulitiplyer you have to say the same about Latice since there
are at least on the marketing slides I have seen identical.
YMHO
Fredrik
 
I agree with Luc. The DSP blocks are just great for a low cost FPGA.
Stratix have the same or similar but you need to pay for them.
Another point that Luc mentioned is the DDR capabilities. There is a
dedicated hardware (DLL and input registers) to facilitate the DDR
interface without needing to waste LUT on it. I like that as well.
Clocking scheme looks good. Great range of freq from analog PLLs.
Normal 4 quadrants. It seems the market for the low cost FPGA is
getting hot with one good new member. ..

paul

Luc Braeckman <luc.braeckman@pandora.be> wrote in message news:<jflke0156m53oldb1laiu7cjuf2ljujgtf@4ax.com>...
Fredrik,

I don't want to start a discussion about the chicken and the egg and..
You are right about Stratix, but Lattice has implemented them in a low
cost device, and there is the advantage. If you don't want to spend
lot's of $$ on features you're not going to use, this ECP-DSP family
is a very good alternative, and the performance ... well look for
yourselve and try a benchmark.
Luc
___
for On 5 Jul 2004 23:11:54 -0700, fredrik_he_lang@hotmail.com
(Fredrik) wrote:

Luc Braeckman <luc.braeckman@pandora.be> wrote in message news:<co4ie010ld9h69mmp8i09l86i5l0uhs13a@4ax.com>...
IMHO, Altera's DSP block is only a multiplier. The MAC block Lattice
is proposing is much richer: reg, mult, pipeline reg, accu, reg. On
top of it, the IO cell has more regs than any other comparable
architecture.
Please have a look at:
http://www.altera.com/products/devices/stratix/features/stx-dsp.html
and then see where Latice got thier ideas from. But you are correct
for the lowcost families Altera (CycloneII) and Xilinx (spartan-3) has
chosen Multipliers rather then DSP blocks. Put if you call Alteras DSP
block a mulitiplyer you have to say the same about Latice since there
are at least on the marketing slides I have seen identical.
YMHO
Fredrik
 
Have any of you tried Lattice's software for their new -EC parts? How close
is it to Xilinx (they share a common heritage)? I'm trying to get a feel
for its quality and stability.

Things should be getting interesting when their 90nm -SC parts come out (vs.
Stratix-II and Virtex-4), especially with their cool DDR I/O interface.
Perhaps Lattice will make a come-back?

--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
 
Paul and Luc,
There is no contridiction, they look good the new Lattice parts, my
point was that the DSP block (stratix) is similar to DSP-blocks in
Lattice. My second point was that the marketing done by Altera for
CycloneII they have never called the embedded multipilers for
DPS-blocks since they as pointed out are not.
The battle for FPGA supremacy continues ...
Cheers
Fredrik
paul_sereno@hotmail.com (Paul Sereno) wrote in message news:<3d7510b4.0407061111.18b75a94@posting.google.com>...
I agree with Luc. The DSP blocks are just great for a low cost FPGA.
Stratix have the same or similar but you need to pay for them.
Another point that Luc mentioned is the DDR capabilities. There is a
dedicated hardware (DLL and input registers) to facilitate the DDR
interface without needing to waste LUT on it. I like that as well.
Clocking scheme looks good. Great range of freq from analog PLLs.
Normal 4 quadrants. It seems the market for the low cost FPGA is
getting hot with one good new member. ..

paul

Luc Braeckman <luc.braeckman@pandora.be> wrote in message news:<jflke0156m53oldb1laiu7cjuf2ljujgtf@4ax.com>...
Fredrik,

I don't want to start a discussion about the chicken and the egg and..
You are right about Stratix, but Lattice has implemented them in a low
cost device, and there is the advantage. If you don't want to spend
lot's of $$ on features you're not going to use, this ECP-DSP family
is a very good alternative, and the performance ... well look for
yourselve and try a benchmark.
Luc
___
for On 5 Jul 2004 23:11:54 -0700, fredrik_he_lang@hotmail.com
(Fredrik) wrote:

Luc Braeckman <luc.braeckman@pandora.be> wrote in message news:<co4ie010ld9h69mmp8i09l86i5l0uhs13a@4ax.com>...
IMHO, Altera's DSP block is only a multiplier. The MAC block Lattice
is proposing is much richer: reg, mult, pipeline reg, accu, reg. On
top of it, the IO cell has more regs than any other comparable
architecture.
Please have a look at:
http://www.altera.com/products/devices/stratix/features/stx-dsp.html
and then see where Latice got thier ideas from. But you are correct
for the lowcost families Altera (CycloneII) and Xilinx (spartan-3) has
chosen Multipliers rather then DSP blocks. Put if you call Alteras DSP
block a mulitiplyer you have to say the same about Latice since there
are at least on the marketing slides I have seen identical.
YMHO
Fredrik
 
Joseph,

I tried the software, and it looks good. As you mentioned, they share
a similar GUI, even the EPIC editor is similar.
Of course the libraries aren't complete yet, but it gives you a good
feeling of the possibilities.

You're right, with the introduction of the 90nm SC parts, I think they
can compete with every other high-end FPGA.

Luc
___

On Tue, 6 Jul 2004 21:18:17 +0000 (UTC), jhallen@TheWorld.com (Joseph
H Allen) wrote:

Have any of you tried Lattice's software for their new -EC parts? How close
is it to Xilinx (they share a common heritage)? I'm trying to get a feel
for its quality and stability.

Things should be getting interesting when their 90nm -SC parts come out (vs.
Stratix-II and Virtex-4), especially with their cool DDR I/O interface.
Perhaps Lattice will make a come-back?
 
continuing the discussion about Lattice's DSP block, I found the
following interesting article:

http://www.fpgajournal.com/articles/20040706_lattice.htm

regards,

paul

Luc Braeckman <luc.braeckman@pandora.be> wrote in message news:<lodne0lvp5eovdjm6v670bcrm4uod7vs1i@4ax.com>...
Joseph,

I tried the software, and it looks good. As you mentioned, they share
a similar GUI, even the EPIC editor is similar.
Of course the libraries aren't complete yet, but it gives you a good
feeling of the possibilities.

You're right, with the introduction of the 90nm SC parts, I think they
can compete with every other high-end FPGA.

Luc
___

On Tue, 6 Jul 2004 21:18:17 +0000 (UTC), jhallen@TheWorld.com (Joseph
H Allen) wrote:

Have any of you tried Lattice's software for their new -EC parts? How close
is it to Xilinx (they share a common heritage)? I'm trying to get a feel
for its quality and stability.

Things should be getting interesting when their 90nm -SC parts come out (vs.
Stratix-II and Virtex-4), especially with their cool DDR I/O interface.
Perhaps Lattice will make a come-back?
 
paul_sereno@hotmail.com (Paul Sereno) wrote in message news:<3d7510b4.0407021019.c3a5df5@posting.google.com>...
I am just wandering if any of you have take a look at the Lattice
FPGAs. I do like the DSP functions.
is out there any serious comparation against SpartanIII and Cyclone?
The local Lattice FAE gave us the low-down. Looks like a decent set
of chips.

One thing we REALLY liked is that if you go with the devices that use
an external configuration EPROM (rather than the family with the
internal config flash), you can use a standard (read: CHEAP) SPI
device, rather than a non-cheap specific config chip.

I've always wondered why Brand A and Brand X continue to use their
expensive config parts. Actually, that's not true -- I know why.
Seriously, what's the point of using a $10 FPGA when the config EPROM
is also $10?

-a
 
"Andy Peters" <Bassman59a@yahoo.com> wrote in message
news:9a2c3a75.0407131029.137e7596@posting.google.com...
paul_sereno@hotmail.com (Paul Sereno) wrote in message
news:<3d7510b4.0407021019.c3a5df5@posting.google.com>...
I am just wandering if any of you have take a look at the Lattice
FPGAs. I do like the DSP functions.
is out there any serious comparation against SpartanIII and Cyclone?

The local Lattice FAE gave us the low-down. Looks like a decent set
of chips.

One thing we REALLY liked is that if you go with the devices that use
an external configuration EPROM (rather than the family with the
internal config flash), you can use a standard (read: CHEAP) SPI
device, rather than a non-cheap specific config chip.

I've always wondered why Brand A and Brand X continue to use their
expensive config parts. Actually, that's not true -- I know why.
Seriously, what's the point of using a $10 FPGA when the config EPROM
is also $10?
Altera has addressed this problem with the Cyclone family - the
configuration devices are quite cheap.

Leon
 
As far as I could discover, this is still a propriatary device, and
therefore you could not use a standard SPI flash instead. If no
competition (read pin/pin compatible replacement) is possible, Altera
could keep up the price as high as they want.
With standard SPI flash, I have the choice of at least 5 different
suppliers, no potentialy delivery problems, and guaranteed lowest
price. Thus driving the total solution cost to a minimum.

Luc

On Tue, 13 Jul 2004 20:52:44 +0100, "Leon Heller"
<leon_heller@hotmail.com> wrote:

"Andy Peters" <Bassman59a@yahoo.com> wrote in message
news:9a2c3a75.0407131029.137e7596@posting.google.com...
paul_sereno@hotmail.com (Paul Sereno) wrote in message
news:<3d7510b4.0407021019.c3a5df5@posting.google.com>...
I am just wandering if any of you have take a look at the Lattice
FPGAs. I do like the DSP functions.
is out there any serious comparation against SpartanIII and Cyclone?

The local Lattice FAE gave us the low-down. Looks like a decent set
of chips.

One thing we REALLY liked is that if you go with the devices that use
an external configuration EPROM (rather than the family with the
internal config flash), you can use a standard (read: CHEAP) SPI
device, rather than a non-cheap specific config chip.

I've always wondered why Brand A and Brand X continue to use their
expensive config parts. Actually, that's not true -- I know why.
Seriously, what's the point of using a $10 FPGA when the config EPROM
is also $10?

Altera has addressed this problem with the Cyclone family - the
configuration devices are quite cheap.

Leon
 
Andy Peters <Bassman59a@yahoo.com> wrote:
: paul_sereno@hotmail.com (Paul Sereno) wrote in message news:<3d7510b4.0407021019.c3a5df5@posting.google.com>...
: > I am just wandering if any of you have take a look at the Lattice
: > FPGAs. I do like the DSP functions.
: > is out there any serious comparation against SpartanIII and Cyclone?

: The local Lattice FAE gave us the low-down. Looks like a decent set
: of chips.

: One thing we REALLY liked is that if you go with the devices that use
: an external configuration EPROM (rather than the family with the
: internal config flash), you can use a standard (read: CHEAP) SPI
: device, rather than a non-cheap specific config chip.

: I've always wondered why Brand A and Brand X continue to use their
: expensive config parts. Actually, that's not true -- I know why.
: Seriously, what's the point of using a $10 FPGA when the config EPROM
: is also $10?

X tries to come up with the XCF Series, also the XCF has still delivery problems.

Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
 
Luc Braeckman wrote:
As far as I could discover, this is still a propriatary device, and
therefore you could not use a standard SPI flash instead. If no
competition (read pin/pin compatible replacement) is possible, Altera
could keep up the price as high as they want.
With standard SPI flash, I have the choice of at least 5 different
suppliers, no potentialy delivery problems, and guaranteed lowest
price. Thus driving the total solution cost to a minimum.

Luc
Still unverified by me, but someone pointed here some time ago that EPCS
devices are indeed a standard device produced by ST (M25Px0). Anyway, if
that's true, Altera has a quite expensive paint... :D

Ricardo
 
I suppose you could use an SPI flash in conjuction with a cheap up like a PIC (some of those are less than a dollar,
and they even have one in a SOT23 package) to undercut the cost of the serial config ROMs.


--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
 
Just FYI, there is an application note on this very topic that demonstrates
how to configure a Xilinx FPGA from an SPI serial Flash using a small CPLD.
The application note is written for CoolRunner-II, but practically any
Xilinx CPLD will do.

XAPP800: Configuring Xilinx FPGAs with SPI Flash Memories Using
CoolRunner-II CPLDs
http://www.xilinx.com/bvdocs/appnotes/xapp800.pdf

While we're on the subject, have you ever wanted to store additional
information in the configuration memory (serial numbers, Ethernet MAC IDs,
MicroBlaze code) and read it after the FPGA configures? If so, the
following application note may be of interest.

XAPP694: Reading User Data from Configuration PROMs
http://www.xilinx.com/bvdocs/appnotes/xapp694.pdf

The two demo designs for the Spartan-3 Starter Kit also demonstrate this
capability.
http://www.xilinx.com/products/spartan3/s3boards.htm#RF

---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3: Make it Your ASIC


"Ray Andraka" <ray@andraka.com> wrote in message
news:40F5AEB8.DDDC48C9@andraka.com...
I suppose you could use an SPI flash in conjuction with a cheap up like a
PIC (some of those are less than a dollar,
and they even have one in a SOT23 package) to undercut the cost of the
serial config ROMs.


--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
 
Of course you can, why not building a complete system just to
configure the FPGA (sic). The idea of a cheap SPI flash directly
connected to the FPGA is very attractive, especially in consumer
application where every cent counts.

Regards,

Luc
___
On Wed, 14 Jul 2004 17:28:59 -0700, "Steven K. Knapp"
<steve.knappNO#SPAM@xilinx.com> wrote:

Just FYI, there is an application note on this very topic that demonstrates
how to configure a Xilinx FPGA from an SPI serial Flash using a small CPLD.
The application note is written for CoolRunner-II, but practically any
Xilinx CPLD will do.

XAPP800: Configuring Xilinx FPGAs with SPI Flash Memories Using
CoolRunner-II CPLDs
http://www.xilinx.com/bvdocs/appnotes/xapp800.pdf

While we're on the subject, have you ever wanted to store additional
information in the configuration memory (serial numbers, Ethernet MAC IDs,
MicroBlaze code) and read it after the FPGA configures? If so, the
following application note may be of interest.

XAPP694: Reading User Data from Configuration PROMs
http://www.xilinx.com/bvdocs/appnotes/xapp694.pdf

The two demo designs for the Spartan-3 Starter Kit also demonstrate this
capability.
http://www.xilinx.com/products/spartan3/s3boards.htm#RF

---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3: Make it Your ASIC


"Ray Andraka" <ray@andraka.com> wrote in message
news:40F5AEB8.DDDC48C9@andraka.com...
I suppose you could use an SPI flash in conjuction with a cheap up like a
PIC (some of those are less than a dollar,
and they even have one in a SOT23 package) to undercut the cost of the
serial config ROMs.


--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
 
"Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com> wrote in message news:<cd4j4e$oeu6@cliff.xsj.xilinx.com>...
Just FYI, there is an application note on this very topic that demonstrates
how to configure a Xilinx FPGA from an SPI serial Flash using a small CPLD.
The application note is written for CoolRunner-II, but practically any
Xilinx CPLD will do.

XAPP800: Configuring Xilinx FPGAs with SPI Flash Memories Using
CoolRunner-II CPLDs
http://www.xilinx.com/bvdocs/appnotes/xapp800.pdf
Yeah, but this solution still requires another part. Perhaps
reasonable if you needed the CPLD for other things, but otherwise it's
not a very good solution. Some boards are overstuffed as it is!

I remember using a 9536 to interface a parallel EPROM to XC4000-series
parts, but that was ages ago, before the G-dsend known as in-system
JTAG-programmable parts ...

--a
 

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