B
B. Joshua Rosen
Guest
I've uploaded a new release of HDLmaker, revision 7.3.3. HDLmaker is an
open source Verilog hierarchy builder for building FPGAs (especially
Xilinx) and ASICs. It creates projects files and scripts for all of the
popular simulation and synthesis tools including XST, Synplify, Precision,
NCsim, VCS, ModelSim. VHDL support has be deprecated in HDLmaker. VHDL
components may be instantiated in Verilog designs but it is no longer
recommended that you use VHDL as the target language as many of the new
features are Verilog only.
http://www.polybus.com/hdlmaker/users_guide/index.htm
open source Verilog hierarchy builder for building FPGAs (especially
Xilinx) and ASICs. It creates projects files and scripts for all of the
popular simulation and synthesis tools including XST, Synplify, Precision,
NCsim, VCS, ModelSim. VHDL support has be deprecated in HDLmaker. VHDL
components may be instantiated in Verilog designs but it is no longer
recommended that you use VHDL as the target language as many of the new
features are Verilog only.
http://www.polybus.com/hdlmaker/users_guide/index.htm