New free Verilog Editor

Hi everybody!

We're launching a new Verilog Editor, with built-in navigation, autocomplete etcetera.

It is free for use for any project size: http://www.VerilogEditor.com

Feel free to try it out, and let me know what you think.

best regards
Philippe

 

[GaborSzakacs]

philippe.faes@sigasi.com wrote:

Hi everybody!

We're launching a new Verilog Editor, with built-in navigation, autocomplete etcetera.

It is free for use for any project size: http://www.VerilogEditor.com

Feel free to try it out, and let me know what you think.

best regards
Philippe

I gave it a quick spin. Autocompletion seems to have some quirks.
For example if I type the following:

if (signal_name == 4'b1111

What I get is:

if (signal_name == 4'b1111')

Note that I got an extra apostrophe in addition to the
close parenthesis. This seems like a bug, especially
since the apostrophe is never used as a single-quote
in Verilog.

The same issue does not happen when I type an apostrophe in
other areas (maybe it just happens within autocomplete parens).

Also I can see that there are templates, and I couldn't figure
out how they work. There's supposed to be a ctrl-space key
binding that brings up options, but it didn't do anything for
me.

Finally I don't see any column editing ability. I often try
to line up things that are not on the left margin. Column
block select makes this easier when creating something like:

seven_segment u7seg
(
.sys_clk (sys_clk),
.reset (reset),
.digits_in (digits_in),
.dpoints_in (dpoints_in),
.blank_in (blank_in),
.digit_drive (digit_drive),
.a_drive (a_drive),
.b_drive (b_drive),
.c_drive (c_drive),
.d_drive (d_drive),
.e_drive (e_drive),
.f_drive (f_drive),
.g_drive (g_drive),
.dp_drive (dp_drive)
);

Syntax highlighting works well. In all it's a good first pass at
an editor, but I suspect that Sigasi is more interested in the
integrated suite of tools than in making a really good editor.

--
Gabor