A
Andrew Ward
Guest
Hevday Logic Ltd has released a new Logic Module with accompanying
software to simplify the use of FPGA technology in prototyping and small
volume applications.
The Hevday Interactive Logic software and Logic Module provides all you
need to design schematic based FPGA designs which can be viewed and
debugged from a TCP/IP connected PC while the circuit is running. The
visibility provided by Interactive Logic provides significant advantages
in understanding circuit operation and debugging your logic circuit designs.
The Interactive Logic software gives you complete control over the
circuit running in the Logic Module. Clock frequencies can be selected
from 10 to 100Mhz, and the circuit can be run, paused or single stepped
one clock at a time. The circuit state, including data, signals and
state machine states can be continuously displayed on the PC screen.
Other advantages of this system include long time scale waveform display
of signals over periods of continuous operation up to 7 days, setting of
breakpoints to pause on predefined conditions for debugging circuit
operation and, in addition to standard timing calculations, a novel
approach for determining maximum allowable clock frequency based on
testing actual circuit functionality.
For more information and to download a free copy of the Interactive
Logic software visit http://www.hevday.com
software to simplify the use of FPGA technology in prototyping and small
volume applications.
The Hevday Interactive Logic software and Logic Module provides all you
need to design schematic based FPGA designs which can be viewed and
debugged from a TCP/IP connected PC while the circuit is running. The
visibility provided by Interactive Logic provides significant advantages
in understanding circuit operation and debugging your logic circuit designs.
The Interactive Logic software gives you complete control over the
circuit running in the Logic Module. Clock frequencies can be selected
from 10 to 100Mhz, and the circuit can be run, paused or single stepped
one clock at a time. The circuit state, including data, signals and
state machine states can be continuously displayed on the PC screen.
Other advantages of this system include long time scale waveform display
of signals over periods of continuous operation up to 7 days, setting of
breakpoints to pause on predefined conditions for debugging circuit
operation and, in addition to standard timing calculations, a novel
approach for determining maximum allowable clock frequency based on
testing actual circuit functionality.
For more information and to download a free copy of the Interactive
Logic software visit http://www.hevday.com