New alternative to CPLD and basic FPGA

[Donato Pace]

Hail, i am an italian student of electronic at italian university..



I have found another method to realize un state finite autome, without
complex circuit, without microprocessors, without FPGA, without logic gates
with feedback of Flip-Flop!!!!!!!!!!!!!!!

My circuit is very simple and it has not affect from problems of alee
statics and dinamics, moreover is very easy to program and the effective
states is only the real states that is necessary for project, without the
problems that offers the Flip Flops and logic gates that obligate the
customer to define all the possible 2^n states that they come produced, of
which an unfortunately only part are really useful to the plan, moreover
because of to these states the circuita complexity increases them, reducing
is the times of execution that the time in order to program chip the
ASIC/FPGA!!!!!!!!!!!!

My circuit uses only one around most common memory with little
components!!!!!!!!



Joke is not one.... I hope that you will take in consideration my plan that
I have already experimented. I would want to sell it.... you are
interested?





Please reply to me.

 

[Zara]

On Fri, 27 Jan 2006 10:58:35 +0100, "Donato Pace"
<donatopace@infinito.it> wrote:

Hail, i am an italian student of electronic at italian university..



I have found another method to realize un state finite autome, without
complex circuit, without microprocessors, without FPGA, without logic gates
with feedback of Flip-Flop!!!!!!!!!!!!!!!

My circuit is very simple and it has not affect from problems of alee
statics and dinamics, moreover is very easy to program and the effective
states is only the real states that is necessary for project, without the
problems that offers the Flip Flops and logic gates that obligate the
customer to define all the possible 2^n states that they come produced, of
which an unfortunately only part are really useful to the plan, moreover
because of to these states the circuita complexity increases them, reducing
is the times of execution that the time in order to program chip the
ASIC/FPGA!!!!!!!!!!!!

My circuit uses only one around most common memory with little
components!!!!!!!!



Joke is not one.... I hope that you will take in consideration my plan that
I have already experimented. I would want to sell it.... you are
interested?





Please reply to me.

Maybe it is something like a fed-back PROM? It sounds such an old
idea... at least 20-30 years old...

 

[Rob Young]

My circuit uses only one around most common memory with little
components!!!!!!!!



Joke is not one.... I hope that you will take in consideration my plan
that
I have already experimented. I would want to sell it.... you are
interested?





Please reply to me.


Maybe it is something like a fed-back PROM? It sounds such an old
idea... at least 20-30 years old...

CY7C235 registered PROM...

 

[Andy Peters]

Rob Young wrote:

My circuit uses only one around most common memory with little
components!!!!!!!!

Joke is not one.... I hope that you will take in consideration my plan
that
I have already experimented. I would want to sell it.... you are
interested?

Please reply to me.


Maybe it is something like a fed-back PROM? It sounds such an old
idea... at least 20-30 years old...


CY7C235 registered PROM...

funny how the ancients always steal your best ideas ...

-a