Netlist simulation

E

ec

Guest
Hi

I want to understand : After netlist is generated
and compiled , in case that the original model includes
component instantiations , do I need a new testbench
that "sees" the whole new generated netlist as "one piece"
without components ?

Thanks
ec
 
A good, well designed testbench should serve both RTL & gate leve with
minimal changes (if any). In VHDL since hierarchical access isn't
allowed usually the tb tries to observe only ports in which case no
change should be required - that's theory. However teams usually use
some form SignalSpy like feature to probe internal nodes, this can
complicate the netlist sim especially if the netlist is a flattenned
one. But it is not that hard to make it work. Other problem can be
timing, but tell us what your actual problem is.

Regards
Ajeetha, CVC
www.noveldv.com

ec wrote:
Hi

I want to understand : After netlist is generated
and compiled , in case that the original model includes
component instantiations , do I need a new testbench
that "sees" the whole new generated netlist as "one piece"
without components ?

Thanks
ec
 

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