Net name "\net" after synthesis?

S

Shenli

Guest
Hi all,

I found sometimes after Design Compiler synthesis, the net name will be
changed to something like \net[0], \net[1]... why?

Best regards,
Davy
 
Several reasons:

Synthesis Tools like Synopsys DC have their optimization settings
default on. When the tool tries to optimizes the design because of this
optimization setting, it modifies the name of the nets/instances/ports
to imply that optimization occur.

Another thing is combinatorial logic without an explicit signal
assignment. Example:

mem_ctrl u0 (
.CS (chip_enable & (cntr == 45)),
.WE (wr_enable),
.A (a_enable),
...
);

Above, an RTL example has been given. When the tool tries to synthesize
the code above, it finds that CS port is driven by a combinatorial
logic (AND gate and a comparator). CS must be finally assigned a
signal. Since you have not given a name to this signal, synthesis tool
tries to give a name like \net for example. If you had coded your RTL
above like:

assign cs_signal = chip_enable & (cntr == 45);

mem_ctrl u0 (
.CS (chip_enable),
....
);

then you would not have seen the names generated internally.

Utku

Shenli yazdi:
Hi all,

I found sometimes after Design Compiler synthesis, the net name will be
changed to something like \net[0], \net[1]... why?

Best regards,
Davy
 
Hi Utku,

I understand, thanks a lot!

Best regards,
Shenli

Utku Özcan wrote:
Several reasons:

Synthesis Tools like Synopsys DC have their optimization settings
default on. When the tool tries to optimizes the design because of this
optimization setting, it modifies the name of the nets/instances/ports
to imply that optimization occur.

Another thing is combinatorial logic without an explicit signal
assignment. Example:

mem_ctrl u0 (
.CS (chip_enable & (cntr == 45)),
.WE (wr_enable),
.A (a_enable),
...
);

Above, an RTL example has been given. When the tool tries to synthesize
the code above, it finds that CS port is driven by a combinatorial
logic (AND gate and a comparator). CS must be finally assigned a
signal. Since you have not given a name to this signal, synthesis tool
tries to give a name like \net for example. If you had coded your RTL
above like:

assign cs_signal = chip_enable & (cntr == 45);

mem_ctrl u0 (
.CS (chip_enable),
...
);

then you would not have seen the names generated internally.

Utku

Shenli yazdi:
Hi all,

I found sometimes after Design Compiler synthesis, the net name will be
changed to something like \net[0], \net[1]... why?

Best regards,
Davy
 

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