Nesting of OVL Assertions in Verilog.

Hi everyone,
I am new to assertion based design and am learning the same using
Accellera supplied OVL libraries. I wish to use assertions to verify
the following condition in my design:

Check if expr1 is true after a specified number of clks after a
specified start event has triggered and as soon as it (expr1) becomes
true, check if expr2 has changed its value by an amount which is within
a specified range (between some specified min/max limits).

I have actually come up with this example which uses a combination of
the 'assert_delta' and 'assert_next' assertions. But, as per a very
good PPT slide (available at www.imit.kth.se/courses/2B1423/F6.ppt), it
is not possible to nest assertions.

Just one more question: Do the Accellera supplied assertions (there are
33 of them) cover *all* possible practical verification cases that one
might come across ?

If anyone of you can tell me how to use these two assertions in
combination to verify a design like the one above, I'd be really
thankful.

Best regards,
Amit.

 

[Ajeetha]

Amit,
You seem to be hitting basic limitations of a non-assertion
language trying to capture assertions. BTW, I don't believe your
statement is true

I am new to assertion based design and am

You are well on course to make effective use of it, keep going!!

Again, can you try SVA/PSL? That should easily solve this.

On

Just one more question: Do the Accellera supplied assertions (there are
33 of them) cover *all* possible practical verification cases that one
might come across ?

Sure not. For example, I know SNPS has added 50+ library elements to
their checker library which encompasses OVL like ones, but coded in
SVA.

Same was true of 0-in, later it was aquired by Mentor, I'm not sure
what the status now is. Cadence also supplies similar library of basic
checks and calls it IAL.

BTW, SNPS also supplies Assertion IPs (free with VCS) for standard
protocols such as PCI/AHB etc. See

$VCS_HOME/aip



HTH
Ajeetha, CVC
www.noveldv.com