Nested ifs, why does one work but not the other?

Sorry about the vague title, I couldn't think of a better way to phrase
this one.

Basically, I made a binary counter in VHDL. My working code is
essentially-

process(clock,delay)
begin
if rising_edge(clock) then
delay<=delay+1;
if delay=3686400 then
delay<=1;
locleds<=locleds+1;
end if;
end if;
end process;

and this works - but

process(clock,delay)
begin
if rising_edge(clock) then
delay<=delay+1;
end if;
if delay=3686400 then
delay<=1;
locleds<=locleds+1;
end if;
end process;

doesnt, it just leaves my LED's all blank. The 3686400, BTW, is because
I'm using a 3.686400Mhz osc.
I'm a bit stumped here.. can anyone help?

Thanks - Alan.

 

First process is ok, infering two registers for delay and locleds, it's
the way you should design.

process(clock,delay)
begin
if rising_edge(clock) then
delay<=delay+1;
end if;
if delay=3686400 then
delay<=1;
locleds<=locleds+1;
end if;
end process;

This process is a bit hard. The second "if" is not clocked, but the
process itself is. This is only in simualtion terms equaly to the first
process. Your synthesis program will have to build a counter that
switches immediately to 1 when reaching the max value and trying to
count exactly one time locleds between reaching max value and setting
the counter back to 1. Neither delay nor locleds are registers but
latches with very odd behavior as the enable of the latches depends on
the value of delay. This is a bit like overclocking a normal circuit.
I have no idea what your synthesis tool realy created but could imagine
no real working HW with the described behavior.

bye Thomas

 

[Peter]

Basically, I made a binary counter in VHDL. My working code is
essentially-

process(clock,delay)
begin
if rising_edge(clock) then
delay<=delay+1;
if delay=3686400 then
delay<=1;
locleds<=locleds+1;
end if;
end if;
end process;

and this works - but

Your first example represents a synchronous logic block and is only
activated on the rising edge of the clock. Therefore "delay" shall be
removed from the sensitivity list.


In your second example, the test of the delay counter is outside the
clocked region.
The second "if" statement is executed on every change on the clock,
both rising and falling edges.

Use the template for synchronous processes shown before in this forum:

Process(clock,reset) -- Only clock and reset, nothing else!
Begin
if reset='1' then
Reset all your signals here..
elsif rising_edge(clock) then
Do what has to be done..
end if;
-- Nothing more here!
End Process;

/Peter