D
Douglas Maxwell
Guest
Hi all,
Does anyone know where I can find information on nested generate
statements? The follow code will not synthesise with Synplify 7.3.1
which supports generate constructs.
-------------------------------------------
module gl_op_select (n_reset_i, clk_i, n_wait_flag_i, select_i,
operand_i, operand_o);
parameter sel_bits = 1,
op_sources = 2,
op_bits = 8;
input n_reset_i;
input clk_i;
input n_wait_flag_i;
input [sel_bits -1 :0] select_i;
input [(op_sources*op_bits) -1 :0] operand_i;
output [op_bits -1 :0] operand_o;
reg [op_bits -1 :0] operand_o;
reg [sel_bits -1 :0] select_int;
genvar i;
generate
if (op_sources > 1)
always@(posedge clk_i or negedge n_reset_i)
if (!n_reset_i)
select_int <= 0;
else
if (n_wait_flag_i)
select_int <= select_i;
endgenerate
generate
for (i = 0; i < op_bits; i = i + 1)
begin:multiple_generates
generate
case (op_sources)
0,1:
always@(operand_i)
operand_o <= operand_i;
2 :
always@(select_int or operand_i or i)
if (select_int)
operand_o <= operand_i[i + op_bits];
else
operand_o <= operand_i;
3 :
always@(select_int or operand_i)
case (select_int)
0 : operand_o <= operand_i;
1 : operand_o <= operand_i[i + op_bits];
default : operand_o <= operand_i[i + (op_bits*2)];
endcase
4:
always@(select_int or operand_i)
case (select_int)
0 : operand_o <= operand_i;
1 : operand_o <= operand_i[i + op_bits];
2 : operand_o <= operand_i[i + (op_bits*2)];
default : operand_o <= operand_i[i + (op_bits*3)];
endcase
5:
always@(select_int or operand_i)
case (select_int)
0 : operand_o <= operand_i;
1 : operand_o <= operand_i[i + op_bits];
2 : operand_o <= operand_i[i + (op_bits*2)];
3 : operand_o <= operand_i[i + (op_bits*3)];
default : operand_o <= operand_i[i + (op_bits*4)];
endcase
6:
always@(select_int or operand_i)
case (select_int)
0 : operand_o <= operand_i;
1 : operand_o <= operand_i[i + op_bits];
2 : operand_o <= operand_i[i + (op_bits*2)];
3 : operand_o <= operand_i[i + (op_bits*3)];
4 : operand_o <= operand_i[i + (op_bits*4)];
default : operand_o <= operand_i[i + (op_bits*5)];
endcase
7:
always@(select_int or operand_i)
case (select_int)
0 : operand_o <= operand_i;
1 : operand_o <= operand_i[i + op_bits];
2 : operand_o <= operand_i[i + (op_bits*2)];
3 : operand_o <= operand_i[i + (op_bits*3)];
4 : operand_o <= operand_i[i + (op_bits*4)];
5 : operand_o <= operand_i[i + (op_bits*5)];
default : operand_o <= operand_i[i + (op_bits*6)];
endcase
8:
always@(select_int or operand_i)
case (select_int)
0 : operand_o <= operand_i;
1 : operand_o <= operand_i[i + op_bits];
2 : operand_o <= operand_i[i + (op_bits*2)];
3 : operand_o <= operand_i[i + (op_bits*3)];
4 : operand_o <= operand_i[i + (op_bits*4)];
5 : operand_o <= operand_i[i + (op_bits*5)];
6 : operand_o <= operand_i[i + (op_bits*6)];
default : operand_o <= operand_i[i + (op_bits*7)];
endcase
endcase
endgenerate
end
endgenerate
endmodule
Does anyone know where I can find information on nested generate
statements? The follow code will not synthesise with Synplify 7.3.1
which supports generate constructs.
-------------------------------------------
module gl_op_select (n_reset_i, clk_i, n_wait_flag_i, select_i,
operand_i, operand_o);
parameter sel_bits = 1,
op_sources = 2,
op_bits = 8;
input n_reset_i;
input clk_i;
input n_wait_flag_i;
input [sel_bits -1 :0] select_i;
input [(op_sources*op_bits) -1 :0] operand_i;
output [op_bits -1 :0] operand_o;
reg [op_bits -1 :0] operand_o;
reg [sel_bits -1 :0] select_int;
genvar i;
generate
if (op_sources > 1)
always@(posedge clk_i or negedge n_reset_i)
if (!n_reset_i)
select_int <= 0;
else
if (n_wait_flag_i)
select_int <= select_i;
endgenerate
generate
for (i = 0; i < op_bits; i = i + 1)
begin:multiple_generates
generate
case (op_sources)
0,1:
always@(operand_i)
operand_o <= operand_i;
2 :
always@(select_int or operand_i or i)
if (select_int)
operand_o <= operand_i[i + op_bits];
else
operand_o <= operand_i;
3 :
always@(select_int or operand_i)
case (select_int)
0 : operand_o <= operand_i;
1 : operand_o <= operand_i[i + op_bits];
default : operand_o <= operand_i[i + (op_bits*2)];
endcase
4:
always@(select_int or operand_i)
case (select_int)
0 : operand_o <= operand_i;
1 : operand_o <= operand_i[i + op_bits];
2 : operand_o <= operand_i[i + (op_bits*2)];
default : operand_o <= operand_i[i + (op_bits*3)];
endcase
5:
always@(select_int or operand_i)
case (select_int)
0 : operand_o <= operand_i;
1 : operand_o <= operand_i[i + op_bits];
2 : operand_o <= operand_i[i + (op_bits*2)];
3 : operand_o <= operand_i[i + (op_bits*3)];
default : operand_o <= operand_i[i + (op_bits*4)];
endcase
6:
always@(select_int or operand_i)
case (select_int)
0 : operand_o <= operand_i;
1 : operand_o <= operand_i[i + op_bits];
2 : operand_o <= operand_i[i + (op_bits*2)];
3 : operand_o <= operand_i[i + (op_bits*3)];
4 : operand_o <= operand_i[i + (op_bits*4)];
default : operand_o <= operand_i[i + (op_bits*5)];
endcase
7:
always@(select_int or operand_i)
case (select_int)
0 : operand_o <= operand_i;
1 : operand_o <= operand_i[i + op_bits];
2 : operand_o <= operand_i[i + (op_bits*2)];
3 : operand_o <= operand_i[i + (op_bits*3)];
4 : operand_o <= operand_i[i + (op_bits*4)];
5 : operand_o <= operand_i[i + (op_bits*5)];
default : operand_o <= operand_i[i + (op_bits*6)];
endcase
8:
always@(select_int or operand_i)
case (select_int)
0 : operand_o <= operand_i;
1 : operand_o <= operand_i[i + op_bits];
2 : operand_o <= operand_i[i + (op_bits*2)];
3 : operand_o <= operand_i[i + (op_bits*3)];
4 : operand_o <= operand_i[i + (op_bits*4)];
5 : operand_o <= operand_i[i + (op_bits*5)];
6 : operand_o <= operand_i[i + (op_bits*6)];
default : operand_o <= operand_i[i + (op_bits*7)];
endcase
endcase
endgenerate
end
endgenerate
endmodule