Nested FOR loops with conditional IF statements

M

Modukuri

Guest
Hi:

I'm using Nested FOR loops with conditional IF statements.The code is
being compiled without any errors.
But,at the end of simulation none of the signals are updated.None of
the loop indices are satic.
I'm not sure if that is the probelm.I would really appreciate any help
in solving this problem.Below is the code,I'm working on.


constant p : integer := 2;
constant blksize : integer := 2;
type p_array is array (0 to 3) of integer range 0 to 255;
signal pvec : p_array := (0 => 1, 1 => 2, 2 => 3, 3 => 4);
signal sdata : data_array;
signal cdata : data_array;
type data_array is array (0 to 7,0 to 7) of std_logic_vector(7 downto
0);
signal data1 : data_array := (others => (others => "00000000"));
signal blks_horiz : integer := 4;
signal blks_verti : integer := 4;
type blk_size is array (0 to 1,0 to 1) of std_logic_vector(7 downto
0);
signal SAD_CMP : blk_size;
signal data_blk1 : blk_size := (others => (others => "00000000"));

process(clk,reset,current_data_in,sdata)
begin
if reset = '1' then
search_blk <= data_blk1;
current_blk <= data_blk1;
SAD_CMP <= data_blk1;

elsif (clk'event and clk ='1') then
for m in 1 to 4 loop
for n in 1 to 4 loop
if (cdata'event) then
for i in ((m-1)*blksize) to ((blksize*m)-1) loop
for j in ((m-1)*blksize) to ((blksize*n)-1) loop
current_blk(i,j) <= cdata(i,j);
for k in 0 to (2*p+1) loop
for l in 0 to (2*p+1) loop
if (sdata'event) then
for x in 0 to (i+pvec(k)) loop
for y in 0 to (j+pvec(l)) loop
search_blk(x,y) <= sdata(x,y);
for u in 0 to 1 loop
for v in 0 to 1 loop
SAD_CMP(u,v) <= search_blk(u,v) - current_blk(u,v);
end loop;
end loop;
end loop;
end loop;
end if;
end loop;
end loop;
end loop;
end loop;
end if;
end loop;
end loop;
end if;
end process;

Thanks for any help.
Modukuri
 
smodukuri@hotmail.com (Modukuri) wrote in message news:<615c881e.0405201556.6d6cff88@posting.google.com>...

I'm using Nested FOR loops with conditional IF statements.The code is
being compiled without any errors.
But,at the end of simulation none of the signals are updated.
Click to expand...
If you want comments, post a usable entity and testbench.

-- Mike Treseler
 
Hi:
Here is the complete and architeture of my block.cdata and sdata
values are getting updated.But the current_blk,search_blk and SDA_CMP
values are all zeros at the end of simulation(I think they are just
holding on to the reset state values).

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use std.textio.all;
use IEEE.std_logic_textio.all;
use work.data.all;

entity PE is
port (search_data1_in : in data_array;
current_data1_in : in data_array;
clk,reset : in std_logic;
SAD_blk : out std_logic_vector(11 downto 0)
);
end PE ;

architecture behave of PE is
constant p : integer := 2;
constant blksize : integer := 2;
type p_array is array (0 to 3) of integer range 0 to 255;
signal pvec : p_array := (0 => 1, 1 => 2, 2 => 3, 3 => 4);
signal search_data_in,search_data1_in1 : data_array;
signal current_data1_in1,current_data_in : data_array;
signal sdata : data_array;
signal cdata : data_array;
signal SAD_BLK_Strobe, s_we,c_we : std_logic;
signal s_ras,s_cas,c_ras,c_cas : std_logic;
signal s_row,s_col,c_row,c_col : integer ;
type data_array is array (0 to 7,0 to 7) of std_logic_vector(7 downto
0);
signal data1 : data_array := (others => (others => "00000000"));
type int_array is array (0 to 7,0 to 7) of integer ;
type un_array is array (0 to 7,0 to 7) of unsigned(7 downto 0);
signal blks_horiz : integer := 4;
signal blks_verti : integer := 4;
type blk_size is array (0 to 1,0 to 1) of std_logic_vector(7 downto
0);
signal SAD_CMP : blk_size;
signal data_blk1 : blk_size := (others => (others => "00000000"));

file sdata_in : text is in "data1.txt"
file cdata_in : text is in "data2.txt"

process
variable inline1 : line;
type Y_array is array (0 to 7,0 to 7) of integer;
type un_array is array(0 to 7,0 to 7) of unsigned(7 down to 0);
variable Y_un :un_array;
variable Y :Y_array;
variable char : character;
begin
for i in 0 to 7 loop
assert not endfile(sdata_in) report "end of file" severity failure;
readline(sdata_in,inline1)
for j in 0 to 7 loop
read(inline1,Y(i,j));
read(inline1,char);
Y_un(i,j) := to_unsigned(Y(i,j),8);
search_data_in(i,j) <= std_logic_vector(Y_un(i,j));
sdata(i,j) <= search_data_in(i,j);
end loop;
end loop;
wait;
end process;

process
variable inline2 : line;
type X_array is array (0 to 7,0 to 7) of integer;
type un_array is array(0 to 7,0 to 7) of unsigned(7 down to 0);
variable X_un :un_array;
variable X :X_array;
variable char : character;
begin
for i in 0 to 7 loop
assert not endfile(cdata_in) report "end of file" severity failure;
readline(cdata_in,inline2)
for j in 0 to 7 loop
read(inline2,X(i,j));
read(inline2,char);
X_un(i,j) := to_unsigned(X(i,j),8);
current_data_in(i,j) <= std_logic_vector(X_un(i,j));
cdata(i,j) <= current_data_in(i,j);
end loop;
end loop;
wait;
end process;

process(clk,reset,cdata,sdata)
begin
if reset = '1' then
search_blk <= data_blk1;
current_blk <= data_blk1;
SAD_CMP <= data_blk1;
elsif (clk'event and clk ='1') then
for m in 1 to 4 loop
for n in 1 to 4 loop
if (cdata'event) then
for i in ((m-1)*blksize) to ((blksize*m)-1) loop
for j in ((m-1)*blksize) to ((blksize*n)-1) loop
current_blk(i,j) <= cdata(i,j);
for k in 0 to (2*p+1) loop
for l in 0 to (2*p+1) loop
if (sdata'event) then
for x in 0 to (i+pvec(k)) loop
for y in 0 to (j+pvec(l)) loop
search_blk(x,y) <= sdata(x,y);
for u in 0 to 1 loop
for v in 0 to 1 loop
SAD_CMP(u,v) <= search_blk(u,v) - current_blk(u,v);
end loop;
end loop;
end loop;
end loop;
end if;
end loop;
end loop;
end loop;
end loop;
end if;
end loop;
end loop;
end if;
end process;

end behave;

Please help me out with this.

Thanks,
Modukuri







mike_treseler@comcast.net (Mike Treseler) wrote in message news:<865ab498.0405211055.5a309e1d@posting.google.com>...
smodukuri@hotmail.com (Modukuri) wrote in message news:<615c881e.0405201556.6d6cff88@posting.google.com>...

I'm using Nested FOR loops with conditional IF statements.The code is
being compiled without any errors.
But,at the end of simulation none of the signals are updated.

If you want comments, post a usable entity and testbench.

-- Mike Treseler
Click to expand...
 
mike_treseler@comcast.net (Mike Treseler) wrote in message
If you want comments, post a usable entity and testbench.
Click to expand...
Modukuri wrote:
Here is the complete and architecture of my block.cdata and sdata
Please help me out with this.
Click to expand...
Be happy to, but I'm still missing source for work.data.lib,
data1.txt, data2.txt and the testbench source.

-- Mike Treseler
-----------------------------------
[tres@localhost tmp]$ vcom pe.vhd
Model Technology ModelSim SE vcom 5.8c Compiler 2004.03 Mar 25 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
-- Loading package numeric_std
-- Loading package textio
-- Loading package std_logic_textio
-- Compiling entity pe
** Error: pe.vhd(10): Unknown identifier 'data_array'.
** Error: pe.vhd(11): Unknown identifier 'data_array'.
** Error: pe.vhd(15): VHDL Compiler exiting
 
Hi, sorry for not providing the source files.Below is the
package,where I defined data_array and the also data files.I'm just
using some random numbers for testing purposes.

------------- package for data_array ---------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;

pacakge data is
type data_array is array (0 to 7,0 to 7) of std_logic_vector(7
downto 0);
end data;

--------------end of package ------------------------

--- files with input data --------

data1.txt

1 2 13 4 5 10 19 6
11 2 17 4 8 12 16 9
12 30 25 15 6 11 5 18
21 5 34 8 17 0 16 24
5 14 9 11 20 26 17 31
18 45 32 10 23 16 7 29
9 27 16 39 43 7 18 27
24 5 16 33 25 13 10 17

data2.txt

3 9 16 4 15 7 11 18
11 22 7 14 12 2 11 14
16 31 35 19 9 13 5 20
12 4 41 23 19 13 18 25
15 21 9 14 24 22 21 32
19 41 32 8 25 16 11 30
10 25 14 41 22 7 19 17
23 7 18 32 25 19 16 27

--- end of data files ----

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use std.textio.all;

entity PE is
port (search_data1_in : in data_array;
current_data1_in : in data_array;
clk,reset : in std_logic;
SAD_blk : out std_logic_vector(11 downto 0)
);
end PE ;

architecture behave of PE is
constant p : integer := 1;
constant blksize : integer := 2;
type p_array is array (0 to 3) of integer range 0 to 255;
signal pvec : p_array := (0 => 1, 1 => 2);
signal search_data_in,search_data1_in1 : data_array;
signal current_data1_in1,current_data_in : data_array;
signal sdata : data_array;
signal cdata : data_array;
signal SAD_BLK_Strobe, s_we,c_we : std_logic;
signal s_ras,s_cas,c_ras,c_cas : std_logic;
signal s_row,s_col,c_row,c_col : integer ;
signal data1 : data_array := (others => (others => "00000000"));
type int_array is array (0 to 7,0 to 7) of integer ;
type un_array is array (0 to 7,0 to 7) of unsigned(7 downto 0);
signal blks_horiz : integer := 4;
signal blks_verti : integer := 4;
type blk_size is array (0 to 1,0 to 1) of std_logic_vector(7 downto
0);
type SAD_array is array(0 to 3,0 to 3) of std_logic_vector(7 downto
0);
signal SAD_CMP : SAD_array;
signal data_blk1 : blk_size := (others => (others => "00000000"));

file sdata_in : text is in "data1.txt"
file cdata_in : text is in "data2.txt"

process
variable inline1 : line;
type Y_array is array (1 to 100,1 to 100) of integer;
type un_array is array(1 to 100,1 to 100) of unsigned(7 down to 0);
variable Y_un :un_array;
variable Y :Y_array;
variable char : character;
begin
for i in 1 to 100 loop
assert not endfile(sdata_in) report "end of file" severity failure;
readline(sdata_in,inline1)
for j in 1 to 100 loop
read(inline1,Y(i,j));
read(inline1,char);
Y_un(i,j) := to_unsigned(Y(i,j),8);
search_data_in(i,j) <= std_logic_vector(Y_un(i,j));
sdata(i,j) <= search_data_in(i,j);
end loop;
end loop;
wait;
end process;

process
variable inline2 : line;
type X_array is array (1 to 100,1 to 100) of integer;
type un_array is array(1 to 100,1 to 100) of unsigned(7 down to 0);
variable X_un :un_array;
variable X :X_array;
variable char : character;
begin
for i in 1 to 100 loop
assert not endfile(cdata_in) report "end of file" severity failure;
readline(cdata_in,inline2)
for j in 1 to 100 loop
read(inline2,X(i,j));
read(inline2,char);
X_un(i,j) := to_unsigned(X(i,j),8);
current_data_in(i,j) <= std_logic_vector(X_un(i,j));
cdata(i,j) <= current_data_in(i,j);
end loop;
end loop;
wait;
end process;

process(clk,reset,cdata,sdata)
variable current_blk : blk_size;
variable search_blk : blk_size;
begin
if reset = '1' then
search_blk := data_blk1;
current_blk := data_blk1;
SAD_CMP <= data_blk1;
elsif (clk'event and clk ='1') then
for m in 1 to 4 loop
for n in 1 to 4 loop
if (cdata'event) then
for i in ((m-1)*blksize) to ((blksize*m)-1) loop
for j in ((m-1)*blksize) to ((blksize*n)-1) loop
current_blk(i,j) := cdata(i,j);
for k in 0 to (2*p-1) loop
for l in 0 to (2*p-1) loop
if (sdata'event) then
for x in ((i-1)+pvec(k)) to (i+pvec(k)) loop
for y in ((j-1)+pvec(l)) to (j+pvec(l)) loop
search_blk(x,y) := sdata(x,y);
for u in 0 to (2*p+1) loop
for v in 0 to (2*p+1) loop
SAD_CMP(u,v) <= search_blk(x,y) - current_blk(i,j);
end loop;
end loop;
end loop;
end loop;
end if;
end loop;
end loop;
end loop;
end loop;
end if;
end loop;
end loop;
end if;
end process;

end behave;


In the last process, SAD_CMP is computing difference between
search_blk and current_blk. Some of the values can be negative,
if the values in search_blk are less than the values in current_blk.I
want absoulte values for all the differences. I tried to use
"abs" function ,but it gave errors saying "no feasible entries for
'abs'" Is there any way I can get just the absoulte values
in SAD_CMP? Can you please give me an idea to get this.

Thanks a lot,
Modukuri













Mike Treseler <mike_treseler@comcast.net> wrote in message news:<As6dnZaXSZrbei3dRVn-jg@comcast.com>...
mike_treseler@comcast.net (Mike Treseler) wrote in message
If you want comments, post a usable entity and testbench.

Modukuri wrote:
Here is the complete and architecture of my block.cdata and sdata
Please help me out with this.

Be happy to, but I'm still missing source for work.data.lib,
data1.txt, data2.txt and the testbench source.

-- Mike Treseler
-----------------------------------
[tres@localhost tmp]$ vcom pe.vhd
Model Technology ModelSim SE vcom 5.8c Compiler 2004.03 Mar 25 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
-- Loading package numeric_std
-- Loading package textio
-- Loading package std_logic_textio
-- Compiling entity pe
** Error: pe.vhd(10): Unknown identifier 'data_array'.
** Error: pe.vhd(11): Unknown identifier 'data_array'.
** Error: pe.vhd(15): VHDL Compiler exiting
Click to expand...
 
smodukuri@hotmail.com (Modukuri) wrote in message news:<615c881e.0405240742.3180c13a@posting.google.com>...

In the last process, SAD_CMP is computing difference between
search_blk and current_blk. Some of the values can be negative,
if the values in search_blk are less than the values in current_blk.I
want absolute values for all the differences. I tried to use
"abs" function ,but it gave errors saying "no feasible entries for
'abs'" Is there any way I can get just the absolute values
in SAD_CMP?
Click to expand...
Using unsigned (or signed) and the numeric_std library functions
will help. See my edits below. I corrected several syntax
and type errors to get your code to compile and load.
It still needs work to run. Which simulator are you using?

# Loading work.data
# Loading work.pe(behave)
VSIM 1> run 1
# ** Error: (vsim-3543) TEXTIO procedure READ (CHARACTER) :
Parameter L of type LINE is empty.
# Time: 0 ns Iteration: 0 Instance: /pe
# ** Fatal: (vsim-3421) Value 8 is out of range 0 to 7.
# Time: 0 ns Iteration: 0 Process: /pe/line__108
File: /evtfs/home/tres/vhdl/play/pe.vhd
# Fatal error at /evtfs/home/tres/vhdl/play/pe.vhd line 122

Use an array of vhdl constants instead
of files for your stimulus. This will eliminate
the errors above and give you more compile-time checking.

Write a few top level comments explaining what you
are trying to do.

Move the signal initializations from the
declaration to the appropriate reset clause.

-- Mike Treseler

------------- package for data_array ---------------
library IEEE;
use IEEE.std_logic_1164.all;
-- use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;

package data is
type data_array is array (0 to 7, 0 to 7) of
unsigned(7 downto 0);
end data;

--------------end of package ------------------------

--- files with input data --------

--data1.txt

--1 2 13 4 5 10 19 6
--11 2 17 4 8 12 16 9
--12 30 25 15 6 11 5 18
--21 5 34 8 17 0 16 24
--5 14 9 11 20 26 17 31
--18 45 32 10 23 16 7 29
--9 27 16 39 43 7 18 27
--24 5 16 33 25 13 10 17

--data2.txt

--3 9 16 4 15 7 11 18
--11 22 7 14 12 2 11 14
--16 31 35 19 9 13 5 20
--12 4 41 23 19 13 18 25
--15 21 9 14 24 22 21 32
--19 41 32 8 25 16 11 30
--10 25 14 41 22 7 19 17
--23 7 18 32 25 19 16 27

--- end of data files ----

library IEEE;
use IEEE.std_logic_1164.all;
-- use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.data.all;

entity PE is
port (search_data1_in : in data_array;
current_data1_in : in data_array;
clk, reset : in std_logic;
SAD_blk : out unsigned(11 downto 0)
);
end PE;

architecture behave of PE is
constant p : integer := 1;
constant blksize : integer := 2;
type p_array is array (0 to 3) of integer range 0 to 255;
signal pvec : p_array
:= (0 => 1, 1 => 2, others => 0);
signal search_data_in, search_data1_in1 : data_array;
signal current_data1_in1, current_data_in : data_array;
signal sdata : data_array;
signal cdata : data_array;
signal SAD_BLK_Strobe, s_we, c_we : std_logic;
signal s_ras, s_cas, c_ras, c_cas : std_logic;
signal s_row, s_col, c_row, c_col : integer;
signal data1 : data_array
:= (others => (others => "00000000"));
type int_array is array (0 to 7, 0 to 7) of integer;
type un_array is array (0 to 7, 0 to 7) of unsigned(7 downto 0);
signal blks_horiz : integer := 4;
signal blks_verti : integer := 4;
type blk_size is array (0 to 1, 0 to 1) of unsigned(7 downto
0);
type SAD_array is array(0 to 3, 0 to 3) of unsigned(7 downto 0);
signal SAD_CMP : SAD_array;
constant sad_init : sad_array := (others => (others => (others => '0')));
signal data_blk1 : blk_size := (others => (others => "00000000"));

file sdata_in : text open read_mode is "data1.txt";
file cdata_in : text open read_mode is "data2.txt";
--file sdata_in : text is in "data1.txt"
--file cdata_in : text is in "data2.txt"
-------------------------------------------------------------------------------
begin
process
variable inline1 : line;
type Y_array is array (1 to 100, 1 to 100) of integer;
type un_array is array(1 to 100, 1 to 100) of unsigned(7 downto 0);
variable Y_un : un_array;
variable Y : Y_array;
variable char : character;
begin
for i in 1 to 100 loop
assert not endfile(sdata_in) report "end of file" severity failure;
readline(sdata_in, inline1);
for j in 1 to 100 loop
read(inline1, Y(i, j));
read(inline1, char);
Y_un(i, j) := to_unsigned(Y(i, j), 8);
search_data_in(i, j) <= unsigned(Y_un(i, j));
sdata(i, j) <= search_data_in(i, j);
end loop;
end loop;
wait;
end process;

process
variable inline2 : line;
type X_array is array (1 to 100, 1 to 100) of integer;
type un_array is array(1 to 100, 1 to 100) of unsigned(7 downto 0);
variable X_un : un_array;
variable X : X_array;
variable char : character;
begin
for i in 1 to 100 loop
assert not endfile(cdata_in) report "end of file" severity failure;
readline(cdata_in, inline2);
for j in 1 to 100 loop
read(inline2, X(i, j));
read(inline2, char);
X_un(i, j) := to_unsigned(X(i, j), 8);
current_data_in(i, j) <= unsigned(X_un(i, j));
cdata(i, j) <= current_data_in(i, j);
end loop;
end loop;
wait;
end process;
-------------------------------------------------------------------------------
process(clk, reset)-- , cdata, sdata)
variable current_blk : blk_size;
variable search_blk : blk_size;
begin
if reset = '1' then
search_blk := data_blk1;
current_blk := data_blk1;
-- SAD_CMP(0 to 1)(0 to 1) <= data_blk1;
sad_cmp <= sad_init;
elsif (clk'event and clk = '1') then
for m in 1 to 4 loop
for n in 1 to 4 loop
if (cdata'event) then
for i in ((m-1)*blksize) to ((blksize*m)-1) loop
for j in ((m-1)*blksize) to ((blksize*n)-1) loop
current_blk(i, j) := cdata(i, j);
for k in 0 to (2*p-1) loop
for l in 0 to (2*p-1) loop
if (sdata'event) then
for x in ((i-1)+pvec(k)) to (i+pvec(k)) loop
for y in ((j-1)+pvec(l))
to (j+pvec(l)) loop
search_blk(x, y) := sdata(x, y);
for u in 0 to (2*p+1) loop
for v in 0 to (2*p+1) loop
SAD_CMP(u, v) <= search_blk(x, y)
- current_blk(i, j);
-------------------------------------------------------------------------------
end loop;
end loop;
end loop;
end loop;
end if;
end loop;
end loop;
end loop;
end loop;
end if;
end loop;
end loop;
end if;
end process;

end behave;
 
HI,
smodukuri@hotmail.com (Modukuri) wrote:
process(clk,reset,current_data_in,sdata)
begin
if reset = '1' then
elsif (clk'event and clk ='1') then
if (cdata'event) then
Click to expand...
This code should simulate fine, if you fix your problems explained by
Mike.
But I wouldn't expect any synthesis tool to produce a netlist which
equals your simulation results.
You mix sequential and combinational signals which is OK for
behavioral code, but not ok for RTL.

A good process is either sequential (only Clk and Reset in the
sensitivity list, only Clk uses 'event) or combinatorial (all inputs
for the process in the sensitivity list, no 'event used).

bye Thomas
 
Hi Mike:

Thanks for all the suggesstions and corrections.I made all the
necessary changes in my code and it is compiling without any
errors.After changing the data type to be unsigned,SAD_CMP values are
not getting updated.During simulation,I'm getting the following
warnings.

** warning NUMERIC_STD.TO_INTEGER : metavalue detected, returning 0
TIME 0 ns iteration : 1 Instance : /pe/dram_s

** warning NUMERIC_STD.TO_INTEGER : metavalue detected, returning 0
TIME 0 ns iteration : 1 Instance : /pe/dram_c


I'm not sure if the conversions between the data types is the
probelm.Could you please help me out with this?

Thanks for all the help,
Modukuri





mike_treseler@comcast.net (Mike Treseler) wrote in message news:<865ab498.0405241455.7f44a8e4@posting.google.com>...
smodukuri@hotmail.com (Modukuri) wrote in message news:<615c881e.0405240742.3180c13a@posting.google.com>...

In the last process, SAD_CMP is computing difference between
search_blk and current_blk. Some of the values can be negative,
if the values in search_blk are less than the values in current_blk.I
want absolute values for all the differences. I tried to use
"abs" function ,but it gave errors saying "no feasible entries for
'abs'" Is there any way I can get just the absolute values
in SAD_CMP?

Using unsigned (or signed) and the numeric_std library functions
will help. See my edits below. I corrected several syntax
and type errors to get your code to compile and load.
It still needs work to run. Which simulator are you using?

# Loading work.data
# Loading work.pe(behave)
VSIM 1> run 1
# ** Error: (vsim-3543) TEXTIO procedure READ (CHARACTER) :
Parameter L of type LINE is empty.
# Time: 0 ns Iteration: 0 Instance: /pe
# ** Fatal: (vsim-3421) Value 8 is out of range 0 to 7.
# Time: 0 ns Iteration: 0 Process: /pe/line__108
File: /evtfs/home/tres/vhdl/play/pe.vhd
# Fatal error at /evtfs/home/tres/vhdl/play/pe.vhd line 122

Use an array of vhdl constants instead
of files for your stimulus. This will eliminate
the errors above and give you more compile-time checking.

Write a few top level comments explaining what you
are trying to do.

Move the signal initializations from the
declaration to the appropriate reset clause.

-- Mike Treseler

------------- package for data_array ---------------
library IEEE;
use IEEE.std_logic_1164.all;
-- use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;

package data is
type data_array is array (0 to 7, 0 to 7) of
unsigned(7 downto 0);
end data;

--------------end of package ------------------------

--- files with input data --------

--data1.txt

--1 2 13 4 5 10 19 6
--11 2 17 4 8 12 16 9
--12 30 25 15 6 11 5 18
--21 5 34 8 17 0 16 24
--5 14 9 11 20 26 17 31
--18 45 32 10 23 16 7 29
--9 27 16 39 43 7 18 27
--24 5 16 33 25 13 10 17

--data2.txt

--3 9 16 4 15 7 11 18
--11 22 7 14 12 2 11 14
--16 31 35 19 9 13 5 20
--12 4 41 23 19 13 18 25
--15 21 9 14 24 22 21 32
--19 41 32 8 25 16 11 30
--10 25 14 41 22 7 19 17
--23 7 18 32 25 19 16 27

--- end of data files ----

library IEEE;
use IEEE.std_logic_1164.all;
-- use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.data.all;

entity PE is
port (search_data1_in : in data_array;
current_data1_in : in data_array;
clk, reset : in std_logic;
SAD_blk : out unsigned(11 downto 0)
);
end PE;

architecture behave of PE is
constant p : integer := 1;
constant blksize : integer := 2;
type p_array is array (0 to 3) of integer range 0 to 255;
signal pvec : p_array
:= (0 => 1, 1 => 2, others => 0);
signal search_data_in, search_data1_in1 : data_array;
signal current_data1_in1, current_data_in : data_array;
signal sdata : data_array;
signal cdata : data_array;
signal SAD_BLK_Strobe, s_we, c_we : std_logic;
signal s_ras, s_cas, c_ras, c_cas : std_logic;
signal s_row, s_col, c_row, c_col : integer;
signal data1 : data_array
:= (others => (others => "00000000"));
type int_array is array (0 to 7, 0 to 7) of integer;
type un_array is array (0 to 7, 0 to 7) of unsigned(7 downto 0);
signal blks_horiz : integer := 4;
signal blks_verti : integer := 4;
type blk_size is array (0 to 1, 0 to 1) of unsigned(7 downto
0);
type SAD_array is array(0 to 3, 0 to 3) of unsigned(7 downto 0);
signal SAD_CMP : SAD_array;
constant sad_init : sad_array := (others => (others => (others => '0')));
signal data_blk1 : blk_size := (others => (others => "00000000"));

file sdata_in : text open read_mode is "data1.txt";
file cdata_in : text open read_mode is "data2.txt";
--file sdata_in : text is in "data1.txt"
--file cdata_in : text is in "data2.txt"
-------------------------------------------------------------------------------
begin
process
variable inline1 : line;
type Y_array is array (1 to 100, 1 to 100) of integer;
type un_array is array(1 to 100, 1 to 100) of unsigned(7 downto 0);
variable Y_un : un_array;
variable Y : Y_array;
variable char : character;
begin
for i in 1 to 100 loop
assert not endfile(sdata_in) report "end of file" severity failure;
readline(sdata_in, inline1);
for j in 1 to 100 loop
read(inline1, Y(i, j));
read(inline1, char);
Y_un(i, j) := to_unsigned(Y(i, j), 8);
search_data_in(i, j) <= unsigned(Y_un(i, j));
sdata(i, j) <= search_data_in(i, j);
end loop;
end loop;
wait;
end process;

process
variable inline2 : line;
type X_array is array (1 to 100, 1 to 100) of integer;
type un_array is array(1 to 100, 1 to 100) of unsigned(7 downto 0);
variable X_un : un_array;
variable X : X_array;
variable char : character;
begin
for i in 1 to 100 loop
assert not endfile(cdata_in) report "end of file" severity failure;
readline(cdata_in, inline2);
for j in 1 to 100 loop
read(inline2, X(i, j));
read(inline2, char);
X_un(i, j) := to_unsigned(X(i, j), 8);
current_data_in(i, j) <= unsigned(X_un(i, j));
cdata(i, j) <= current_data_in(i, j);
end loop;
end loop;
wait;
end process;
-------------------------------------------------------------------------------
process(clk, reset)-- , cdata, sdata)
variable current_blk : blk_size;
variable search_blk : blk_size;
begin
if reset = '1' then
search_blk := data_blk1;
current_blk := data_blk1;
-- SAD_CMP(0 to 1)(0 to 1) <= data_blk1;
sad_cmp <= sad_init;
elsif (clk'event and clk = '1') then
for m in 1 to 4 loop
for n in 1 to 4 loop
if (cdata'event) then
for i in ((m-1)*blksize) to ((blksize*m)-1) loop
for j in ((m-1)*blksize) to ((blksize*n)-1) loop
current_blk(i, j) := cdata(i, j);
for k in 0 to (2*p-1) loop
for l in 0 to (2*p-1) loop
if (sdata'event) then
for x in ((i-1)+pvec(k)) to (i+pvec(k)) loop
for y in ((j-1)+pvec(l))
to (j+pvec(l)) loop
search_blk(x, y) := sdata(x, y);
for u in 0 to (2*p+1) loop
for v in 0 to (2*p+1) loop
SAD_CMP(u, v) <= search_blk(x, y)
- current_blk(i, j);
-------------------------------------------------------------------------------
end loop;
end loop;
end loop;
end loop;
end if;
end loop;
end loop;
end loop;
end loop;
end if;
end loop;
end loop;
end if;
end process;

end behave;
Click to expand...
 
Modukuri wrote:
Hi Mike:

Thanks for all the suggesstions and corrections.I made all the
necessary changes in my code and it is compiling without any
errors.After changing the data type to be unsigned,SAD_CMP values are
not getting updated.During simulation,I'm getting the following
warnings.

** warning NUMERIC_STD.TO_INTEGER : metavalue detected, returning 0
TIME 0 ns iteration : 1 Instance : /pe/dram_s

** warning NUMERIC_STD.TO_INTEGER : metavalue detected, returning 0
TIME 0 ns iteration : 1 Instance : /pe/dram_c
Click to expand...
This is a common problem when you do type conversions in combinational
logic. At time=0, std_logic_vector and unsigned signals will have a
value of 'U'. There is no equivalent integer, hence the warning. There
are at least 3 ways of dealing with this:

1. Ignore all warnings issued at time=0. This is obviously the simplest.

2. Assign initial values to all signals used in conversions. This will
get rid of the warnings but will cause a mismatch between synthesis and
simulation. It also masks problems with signals that don't get
initialized properly by your code.

3. Turn off warnings at time=0 in your simulator. In ModelSim, you can
turn off warnings (don't remember the syntax), issue a 'run 0 ns'
command to flush the warnings, and turn warnings on again.

--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com
 
Hi Mike and Thomas as you stated I'm having problems by placing 'event
on cdata and sdata.

As I explained in my previous post,the SAD_CMP values are not getting
updated.
Regardless of the warnings the simulator(ModelSim from Mentor
graphic's Model tech),I placed a test signal after every loop and I
figured out that the simulator is not responding to the statement
---- "if(cdata'event) then".The test signal failed at this
point.So,I'm sure that the above statement is not working.
I was suggested to generate two signals cdata_event and sdata_event to
use in the process.But that was of no help too.


I add the following to my code to generate sdata_event and
cdata_event.

--data_array is from the pacakege I had defined earlier-----
signal data1 : data_array := (others => (others => "00000000"));
signal cdata_old,sdata_old : data_array;
signal cdata_event,sdata_event : data_array; --I'm not sure about this
declaration. Should this be std_logic???? Please correct me.

process(reset,clk)
begin
if reset = '1' then
cdata <= data1;
sdata <= data1;
elsif (clk'event and clk = '1') then
for i in 0 to 7 loop
for j in 0 to 7 loop
cdata(i,j) <= current_data_in(i,j);
sdata(i,j) <= search_data_in(i,j);
end loop;
end loop;
end if;
end process;

process(reset,clk)
begin
if reset = '1' then
cdata_old <= data1;
sdata_old <= data1;
cdata_event <= data1;
sdata_ecent <= data1;
elsif (clk'event and clk = '1') then
for i in 0 to 7 loop
for j in 0 to 7 loop
cdata_old(i,j) <= cdata(i,j);
sdata_old(i,j) <= sdata(i,j);
cdata_event(i,j) <= cdata_old(i,j) xnor cdata(i,j);
sdata_event(i,j) <= sdata_old(i,j) xnor sdata(i,j);
end loop;
end loop;
end if;
end process;

process(clk,reset,cdata_event,sdata_event)
variable current_blk : blk_size;
variable search_blk : blk_size;
begin
if reset = '1' then
search_blk := data_blk1;
current_blk := data_blk1;
SAD_CMP <= SAD_ini;
elsif (clk'event and clk ='1') then
for m in 1 to 4 loop
for n in 1 to 4 loop
if (cdata_event'event) then
for i in ((m-1)*blksize) to ((blksize*m)-1) loop
for j in ((n-1)*blksize) to ((blksize*n)-1) loop
current_blk(i,j) := cdata(i,j);
for k in 0 to (2*p-1) loop
for l in 0 to (2*p-1) loop
if (sdata_event'event) then
for x in ((i-1)+pvec(k)) to (i+pvec(k)) loop
for y in ((j-1)+pvec(l)) to (j+pvec(l)) loop
search_blk(x,y) := sdata(x,y);
for u in 0 to (2*p+1) loop
for v in 0 to (2*p+1) loop
SAD_CMP(u,v) <= search_blk(x,y) - current_blk(i,j); -- Does
this statement hold good.That is can I use different
indices(u,v),(x,Y) and (i,j)
end loop;
end loop;
end loop;
end loop;
end if;
end loop;
end loop;
end loop;
end loop;
end if;
end loop;
end loop;
end if;
end process;

I'm not very good at VHDL programming.Just learning and using it for
my project.I have been stuck on this for sometime and really need your
valuable suggesstions to move forward.Please help!!

Thanks,
Modukuri






usenet_10@stanka-web.de (Thomas Stanka) wrote in message news:<ef424d2c.0405242259.72788abd@posting.google.com>...
HI,
smodukuri@hotmail.com (Modukuri) wrote:

process(clk,reset,current_data_in,sdata)
begin
if reset = '1' then
elsif (clk'event and clk ='1') then
if (cdata'event) then

This code should simulate fine, if you fix your problems explained by
Mike.
But I wouldn't expect any synthesis tool to produce a netlist which
equals your simulation results.
You mix sequential and combinational signals which is OK for
behavioral code, but not ok for RTL.

A good process is either sequential (only Clk and Reset in the
sensitivity list, only Clk uses 'event) or combinatorial (all inputs
for the process in the sensitivity list, no 'event used).

bye Thomas
Click to expand...
 
Hello,

first I like to state, that a news (or email) is far better readable
if you avoid textabove fullquote below and quote inside the text
(delting unneccessary lines)

smodukuri@hotmail.com (Modukuri) wrote:
I was suggested to generate two signals cdata_event and sdata_event to
use in the process.But that was of no help too.
Click to expand...
You started getting big steps towart your goal, but still didn't
understand what I wrote about PROCESSes.

process(reset,clk)
Click to expand...
good

cdata_event(i,j) <= cdata_old(i,j) xnor cdata(i,j);
sdata_event(i,j) <= sdata_old(i,j) xnor sdata(i,j);
Click to expand...
Seems to be good.

process(clk,reset,cdata_event,sdata_event)
elsif (clk'event and clk ='1') then
if (cdata_event'event) the
Click to expand...
Still the old error.

A good process is either sequential (only Clk and Reset in the
sensitivity list, only Clk uses 'event) or combinatorial (all inputs
for the process in the sensitivity list, no 'event used).
Click to expand...
please read again and understand.

The sollution could be instead of
if Rising_Edge(Signal) then -- same as Signal'event and Signal='1'
use
Signal_SR<=Signal_SR&Signal;
if Signal_SR="01" then -- Rising Edge

Your sollution with XOR is as good as well.

bye Thomas
 
Thanks for all of your valuable suggesstions.
My code is working fine for an 8x8 array.But,when I started forcing
the actual data (it is an 144x176 array), the system is not
responding.I tried the same code for different array sizes.It worked
fine.I'm guessing that my simulator (ModelSim) is unable to handlw
such a big array. Is there any way to get this working?? Here is the
code.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.data.all;

entity PE is

port (search_data1_in : in data_array;
current_data1_in : in data_array;
clk,reset : in std_logic;
SAD_blk : out integer
);
end PE ;

architecture BEHAVE of PE is

constant p : integer := 2;
constant blksize : integer := 4;
constant num_cols : integer := 144;
constant num_rows : integer := 176;
type p_array is array (0 to 3) of integer;
signal pvec : p_array := (0 => 1,1 => 2,2 => 3,3 => 4);
signal search_data_in,search_data1_in1 : data_array;
signal current_data1_in1,current_data_in: data_array;
signal sdata : data_array;
signal cdata : data_array;
signal s_we,c_we : std_logic;
signal s_ras,s_cas,c_ras,c_cas : std_logic;
signal s_row,s_col,c_row,c_col : integer;
signal s_address,c_address : std_logic_vector(15 downto 0);
signal data1 : data_array := (others => (others => 0));
signal blks_horiz : integer := num_cols/4;
signal blks_verti : integer := num_rows/4;
type blk_size is array (0 to 3,0 to 3) of integer;
signal SAD_CMP : data_array ;
signal SAD_ini : data_array := (others => (others => 0));
signal cblk : data_array := (others => (others => 0));
signal sblk : data_array := (others => (others => 0));
signal data_blk1 : blk_size := (others => (others => 0));
signal test : std_logic ;


file sdata_in : text is in
"/export/home1/smodukur/Thesis/Ak3Decimal.txt";
file cdata_in : text is in
"/export/home1/smodukur/Thesis/Ak4Decimal.txt";

component S_DRAM
port(s_address : in std_logic_vector(15 downto 0);
clk,reset : in std_logic;
s_we : in std_logic;
s_ras,s_cas : in std_logic;
s_row,s_col : out integer;
search_data_in : in data_array;
search_data_out : out data_array
);
end component;

component C_DRAM
port(c_address : in std_logic_vector(15 downto 0);
clk,reset : in std_logic;
c_we : in std_logic;
c_ras,c_cas : in std_logic;
c_row,c_col : out integer;
current_data_in : in data_array;
current_data_out : out data_array
);
end component;

begin


DRAM_S : S_DRAM port map(s_address => s_address, clk => clk, reset =>
reset, s_we => s_we, s_ras => s_ras, s_cas => s_cas, s_row => s_row,
s_col => s_col, search_data_in => search_data_in, search_data_out =>
search_data1_in1);

DRAM_C : C_DRAM port map(c_address => c_address, clk => clk, reset
=> reset, c_we => c_we,c_ras => c_ras,c_cas => c_cas, c_row => c_row,
c_col => c_col, current_data_in => current_data_in, current_data_out
=> current_data1_in1);



process
type Y_array is array (0 to 143,0 to 175) of integer ;
variable Y : Y_array;
variable inline : line;
variable char : character;
begin
for i in 0 to 143 loop
assert not endfile(sdata_in) report "Premature end of file"
severity failure;
readline(sdata_in,inline);
for j in 0 to 175 loop
read(inline, Y(i,j));
read(inline,char);
search_data_in(i,j) <= Y(i,j);
end loop;
end loop;
wait;
end process;


process
type X_array is array (0 to 143,0 to 175) of integer ;
variable X : X_array;
variable inline : line;
variable char : character;
begin
for i in 0 to 143 loop
assert not endfile(cdata_in) report "Premature end of file"
severity failure;
readline(cdata_in,inline);
for j in 0 to 175 loop
read(inline,X(i,j));
read(inline,char);
current_data_in(i,j) <= X(i,j);
end loop;
end loop;
wait;
end process;

process(reset,clk)
begin
if reset = '1' then
sdata <= data1;
cdata <= data1;
elsif (clk'event and clk = '1') then
for i in 0 to 143 loop
for j in 0 to 175 loop
sdata(i,j) <= search_data_in(i,j);
cdata(i,j) <= current_data_in(i,j);
end loop;
end loop;
end if;
end process;

process(clk,reset,sdata,cdata)
variable current_blk : data_array;
variable search_blk : data_array;
begin
if reset = '1' then
current_blk := data1;
search_blk := data1;
SAD_CMP <= SAD_ini;
elsif (clk'event and clk = '1') then
for m in 1 to 36 loop
for n in 1 to 44 loop
for i in ((m-1)*blksize) to ((blksize*m)-1) loop
for j in ((n-1)*blksize) to ((blksize*n)-1) loop
current_blk(i,j) := cdata(i,j);
cblk(i,j) <= current_blk(i,j);
for k in 0 to 3 loop
for l in 0 to 3 loop
for x in ((i-1)+pvec(k)) to ((i+pvec(k))) loop
for y in ((j-1)+pvec(l)) to ((j+pvec(l))) loop
if (x <= 143 and y <= 175) then
search_blk(x,y) := sdata(x,y);
sblk(x,y) <= search_blk(x,y);
for u in 0 to 143 loop
for v in 0 to 175 loop
if (sblk(u,v) >= cblk(u,v)) then
SAD_CMP(u,v) <= sblk(u,v) - cblk(u,v);
else
SAD_CMP(u,v) <= cblk(u,v) - sblk(u,v);
end if;
end loop;
end loop;
end if;
end loop;
end loop;
end loop;
end loop;
end loop;
end loop;
end loop;
end loop;
end if;
end process;

end behave;

I really appreciate any ideas/suggesstions in solving this problem.

one more question: In the last process all the loop indices are
dependent on one another.Is there any better way to frame the loops
inorder to eliminate too many nested loops?

Thanks,
Modukuri







usenet_10@stanka-web.de (Thomas Stanka) wrote in message news:<ef424d2c.0405260139.53dfdc11@posting.google.com>...
Hello,

first I like to state, that a news (or email) is far better readable
if you avoid textabove fullquote below and quote inside the text
(delting unneccessary lines)

smodukuri@hotmail.com (Modukuri) wrote:
I was suggested to generate two signals cdata_event and sdata_event to
use in the process.But that was of no help too.

You started getting big steps towart your goal, but still didn't
understand what I wrote about PROCESSes.

process(reset,clk)

good

cdata_event(i,j) <= cdata_old(i,j) xnor cdata(i,j);
sdata_event(i,j) <= sdata_old(i,j) xnor sdata(i,j);

Seems to be good.

process(clk,reset,cdata_event,sdata_event)
elsif (clk'event and clk ='1') then
if (cdata_event'event) the

Still the old error.

A good process is either sequential (only Clk and Reset in the
sensitivity list, only Clk uses 'event) or combinatorial (all inputs
for the process in the sensitivity list, no 'event used).

please read again and understand.

The sollution could be instead of
if Rising_Edge(Signal) then -- same as Signal'event and Signal='1'
use
Signal_SR<=Signal_SR&Signal;
if Signal_SR="01" then -- Rising Edge

Your sollution with XOR is as good as well.

bye Thomas
Click to expand...
 
Hi Modukuri,

To be able to give you a good answer, it is better if you can explain
what do you want to do with your entity.

If I have well understand your big for loop, that must compare the
content of 2 memory bank and give the delta into an array SAD_CMP.
That's correct, doesn't it ?

Then some questions: do you really needs the delta value, or you
interesting only by fact that values are egal or not ?

If only the last is your objective, you can use the logic comparator
'xor' between two buses, instead of use the substraction (that is more a
sw approch). The bit comparator give best result in case of bus management.
You must keep in mind that convertion to integer is limited to 32-bit
buses maximum, and that mathematical operators are limited too (in
aspect of type size handle).

With the 'xor' operator, you are not limited by bus size.

Another comment, don't forget that bus can be equivalent to a
'flattened' array.
In your package definition you give:
type data_array is array (0 to 7,0 to 7) of std_logic_vector(7 downto 0);

That is equivalent to have a bus of std_logic_vector((8*8*8)-1 downto 0)
= std_logic_vector(511 downto 0)

Rgrds,
JaI

Modukuri wrote:

Thanks for all of your valuable suggesstions.
My code is working fine for an 8x8 array.But,when I started forcing
the actual data (it is an 144x176 array), the system is not
responding.I tried the same code for different array sizes.It worked
fine.I'm guessing that my simulator (ModelSim) is unable to handlw
such a big array. Is there any way to get this working?? Here is the
code.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.data.all;

entity PE is

port (search_data1_in : in data_array;
current_data1_in : in data_array;
clk,reset : in std_logic;
SAD_blk : out integer
);
end PE ;

architecture BEHAVE of PE is

constant p : integer := 2;
constant blksize : integer := 4;
constant num_cols : integer := 144;
constant num_rows : integer := 176;
type p_array is array (0 to 3) of integer;
signal pvec : p_array := (0 => 1,1 => 2,2 => 3,3 => 4);
signal search_data_in,search_data1_in1 : data_array;
signal current_data1_in1,current_data_in: data_array;
signal sdata : data_array;
signal cdata : data_array;
signal s_we,c_we : std_logic;
signal s_ras,s_cas,c_ras,c_cas : std_logic;
signal s_row,s_col,c_row,c_col : integer;
signal s_address,c_address : std_logic_vector(15 downto 0);
signal data1 : data_array := (others => (others => 0));
signal blks_horiz : integer := num_cols/4;
signal blks_verti : integer := num_rows/4;
type blk_size is array (0 to 3,0 to 3) of integer;
signal SAD_CMP : data_array ;
signal SAD_ini : data_array := (others => (others => 0));
signal cblk : data_array := (others => (others => 0));
signal sblk : data_array := (others => (others => 0));
signal data_blk1 : blk_size := (others => (others => 0));
signal test : std_logic ;


file sdata_in : text is in
"/export/home1/smodukur/Thesis/Ak3Decimal.txt";
file cdata_in : text is in
"/export/home1/smodukur/Thesis/Ak4Decimal.txt";

component S_DRAM
port(s_address : in std_logic_vector(15 downto 0);
clk,reset : in std_logic;
s_we : in std_logic;
s_ras,s_cas : in std_logic;
s_row,s_col : out integer;
search_data_in : in data_array;
search_data_out : out data_array
);
end component;

component C_DRAM
port(c_address : in std_logic_vector(15 downto 0);
clk,reset : in std_logic;
c_we : in std_logic;
c_ras,c_cas : in std_logic;
c_row,c_col : out integer;
current_data_in : in data_array;
current_data_out : out data_array
);
end component;

begin


DRAM_S : S_DRAM port map(s_address => s_address, clk => clk, reset =
reset, s_we => s_we, s_ras => s_ras, s_cas => s_cas, s_row => s_row,
s_col => s_col, search_data_in => search_data_in, search_data_out =
search_data1_in1);

DRAM_C : C_DRAM port map(c_address => c_address, clk => clk, reset
=> reset, c_we => c_we,c_ras => c_ras,c_cas => c_cas, c_row => c_row,
c_col => c_col, current_data_in => current_data_in, current_data_out
=> current_data1_in1);



process
type Y_array is array (0 to 143,0 to 175) of integer ;
variable Y : Y_array;
variable inline : line;
variable char : character;
begin
for i in 0 to 143 loop
assert not endfile(sdata_in) report "Premature end of file"
severity failure;
readline(sdata_in,inline);
for j in 0 to 175 loop
read(inline, Y(i,j));
read(inline,char);
search_data_in(i,j) <= Y(i,j);
end loop;
end loop;
wait;
end process;


process
type X_array is array (0 to 143,0 to 175) of integer ;
variable X : X_array;
variable inline : line;
variable char : character;
begin
for i in 0 to 143 loop
assert not endfile(cdata_in) report "Premature end of file"
severity failure;
readline(cdata_in,inline);
for j in 0 to 175 loop
read(inline,X(i,j));
read(inline,char);
current_data_in(i,j) <= X(i,j);
end loop;
end loop;
wait;
end process;

process(reset,clk)
begin
if reset = '1' then
sdata <= data1;
cdata <= data1;
elsif (clk'event and clk = '1') then
for i in 0 to 143 loop
for j in 0 to 175 loop
sdata(i,j) <= search_data_in(i,j);
cdata(i,j) <= current_data_in(i,j);
end loop;
end loop;
end if;
end process;

process(clk,reset,sdata,cdata)
variable current_blk : data_array;
variable search_blk : data_array;
begin
if reset = '1' then
current_blk := data1;
search_blk := data1;
SAD_CMP <= SAD_ini;
elsif (clk'event and clk = '1') then
for m in 1 to 36 loop
for n in 1 to 44 loop
for i in ((m-1)*blksize) to ((blksize*m)-1) loop
for j in ((n-1)*blksize) to ((blksize*n)-1) loop
current_blk(i,j) := cdata(i,j);
cblk(i,j) <= current_blk(i,j);
for k in 0 to 3 loop
for l in 0 to 3 loop
for x in ((i-1)+pvec(k)) to ((i+pvec(k))) loop
for y in ((j-1)+pvec(l)) to ((j+pvec(l))) loop
if (x <= 143 and y <= 175) then
search_blk(x,y) := sdata(x,y);
sblk(x,y) <= search_blk(x,y);
for u in 0 to 143 loop
for v in 0 to 175 loop
if (sblk(u,v) >= cblk(u,v)) then
SAD_CMP(u,v) <= sblk(u,v) - cblk(u,v);
else
SAD_CMP(u,v) <= cblk(u,v) - sblk(u,v);
end if;
end loop;
end loop;
end if;
end loop;
end loop;
end loop;
end loop;
end loop;
end loop;
end loop;
end loop;
end if;
end process;

end behave;

I really appreciate any ideas/suggesstions in solving this problem.

one more question: In the last process all the loop indices are
dependent on one another.Is there any better way to frame the loops
inorder to eliminate too many nested loops?

Thanks,
Modukuri







usenet_10@stanka-web.de (Thomas Stanka) wrote in message news:<ef424d2c.0405260139.53dfdc11@posting.google.com>...


Hello,

first I like to state, that a news (or email) is far better readable
if you avoid textabove fullquote below and quote inside the text
(delting unneccessary lines)

smodukuri@hotmail.com (Modukuri) wrote:


I was suggested to generate two signals cdata_event and sdata_event to
use in the process.But that was of no help too.


You started getting big steps towart your goal, but still didn't
understand what I wrote about PROCESSes.



process(reset,clk)


good



cdata_event(i,j) <= cdata_old(i,j) xnor cdata(i,j);
sdata_event(i,j) <= sdata_old(i,j) xnor sdata(i,j);


Seems to be good.



process(clk,reset,cdata_event,sdata_event)
elsif (clk'event and clk ='1') then
if (cdata_event'event) the


Still the old error.



A good process is either sequential (only Clk and Reset in the
sensitivity list, only Clk uses 'event) or combinatorial (all inputs
for the process in the sensitivity list, no 'event used).


please read again and understand.

The sollution could be instead of
if Rising_Edge(Signal) then -- same as Signal'event and Signal='1'
use
Signal_SR<=Signal_SR&Signal;
if Signal_SR="01" then -- Rising Edge

Your sollution with XOR is as good as well.

bye Thomas
Click to expand...
 
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