nested/cascaded conditional operators

J

Jason Zheng

Guest
I have seen many papers suggesting that we shall avoid using nested
conditional operators, and use if/else statements instead. Does anyone
know why this is recommended, besides clarity and ease of reading?
 
Jason Zheng wrote:
I have seen many papers suggesting that we shall avoid using nested
conditional operators, and use if/else statements instead. Does anyone
know why this is recommended, besides clarity and ease of reading?
Click to expand...
I don't know.

There is a definite advantage to using conditional operators. If/else
statements can give overly optimistic results when the condition is X,
treating it as false instead of the worst case. This could hide a bug
during simulation. The conditional operator will not treat the X
condition optimistically. It will produce an X result for any bits
where the true and false results disagree.

Nested conditional operators can be hard to read. Breaking it up into
multiple lines, with proper indentation to show the nesting, can solve
that.
 
sharp@cadence.com wrote:
Jason Zheng wrote:

I have seen many papers suggesting that we shall avoid using nested
conditional operators, and use if/else statements instead. Does anyone
know why this is recommended, besides clarity and ease of reading?


I don't know.

There is a definite advantage to using conditional operators. If/else
statements can give overly optimistic results when the condition is X,
treating it as false instead of the worst case. This could hide a bug
during simulation. The conditional operator will not treat the X
condition optimistically. It will produce an X result for any bits
where the true and false results disagree.

Nested conditional operators can be hard to read. Breaking it up into
multiple lines, with proper indentation to show the nesting, can solve
that.

I have heard that conditional operators tend to synthesize to muxes,
Click to expand...
whereas if/else statements give you more optimal logic. Is that true?
 
sharp@cadence.com wrote:
Jason Zheng wrote:

I have seen many papers suggesting that we shall avoid using nested
conditional operators, and use if/else statements instead. Does anyone
know why this is recommended, besides clarity and ease of reading?


I don't know.

There is a definite advantage to using conditional operators. If/else
statements can give overly optimistic results when the condition is X,
treating it as false instead of the worst case. This could hide a bug
during simulation. The conditional operator will not treat the X
condition optimistically. It will produce an X result for any bits
where the true and false results disagree.
Click to expand...
This brought up a point of pre- and post-synthesis mismatch. I tested
this piece of code with synplify pro and xst:

wire A,B,C,SEL;

assign C = SEL ? A : B;

In my test bench, I feed 0 and 0 to A and B, but 1'bx to SEL. In
pre-synthesis functional simulation, I get 0 for C. However, in
post-synthesis simulation, I get 1'bx for C. So that proved that a
simulation mismatch could be produced with conditional operators if care
is not taken.
 
Jason Zheng wrote:
sharp@cadence.com wrote:

Jason Zheng wrote:

I have seen many papers suggesting that we shall avoid using nested
conditional operators, and use if/else statements instead. Does anyone
know why this is recommended, besides clarity and ease of reading?



I don't know.

There is a definite advantage to using conditional operators. If/else
statements can give overly optimistic results when the condition is X,
treating it as false instead of the worst case. This could hide a bug
during simulation. The conditional operator will not treat the X
condition optimistically. It will produce an X result for any bits
where the true and false results disagree.


This brought up a point of pre- and post-synthesis mismatch. I tested
this piece of code with synplify pro and xst:

wire A,B,C,SEL;

assign C = SEL ? A : B;

In my test bench, I feed 0 and 0 to A and B, but 1'bx to SEL. In
pre-synthesis functional simulation, I get 0 for C. However, in
post-synthesis simulation, I get 1'bx for C. So that proved that a
simulation mismatch could be produced with conditional operators if care
is not taken.
Nevermind, it wasn't a mismatch. The two answers agreed after I fixed a
Click to expand...
reset problem.
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top