negative indexes

[valentin tihomirov]

The following snippet of code is working only for widths > 2. Here is the
description of the process. The WIDTH specifies a fifo's input vector width.
A buffer of WIDTH-1 bits wide forestalls the input of fifo. Bits are coming
one-by-one from Rx and are shifted into buffer. When buffer is loaded, fifo
reads the vector, whereby upper bit is taken directly from Rx line.

SHIFT_IN: process(CLK, RESET, SHIFTING, Rx)
variable Buf: std_logic_vector(WIDTH-2 downto 0);
begin

FIFO_IN <= Rx & Buf(WIDTH-2 downto 0);

if Rising_Edge(CLK) and ENABLE = '1' then
if SHIFTING then
Buf := Rx & Buf(WIDTH-2 downto 1);
end if;
end if;

end process;



WIDTH = 1 is not allowed because we get vector(-1 downto 0). Buf should have
length 0 in this case. Compiler sumbles at Rx & Buf(0 downto 1) when
WIDTH=2. The situations like
for I := 0 downto 1 do
are handeled in any general-purpose programming language by not entering
into the loop. What is the proper way to describe the HW in VHDL? The
process must work for WIDTH > 0.

 

[Jim Lewis]

First a general note, if FIFO_IN creates a wire,
make it separate from the process and make BUF a
signal.


For Width = 1, you only pass RX to FIFO_IN.
This means BUF does nothing and the following
assignment is an error since BUF is of size 0
and the resulting array is of size 1:
Buf := Rx & Buf(0 downto 1);

Hence, wrap it in a if-generate block and turn
it off if width=1.

For Width=2, you should be ok with all of your code.
Null ranges should be accepted by a simulator in the
way you have used them.

If the synthesis tool is harassing you about null
ranges, then you will have to wrap the special handling
for Width=2 and Width=1 in separate if-generate blocks.

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~



valentin tihomirov wrote:

The following snippet of code is working only for widths > 2. Here is the
description of the process. The WIDTH specifies a fifo's input vector width.
A buffer of WIDTH-1 bits wide forestalls the input of fifo. Bits are coming
one-by-one from Rx and are shifted into buffer. When buffer is loaded, fifo
reads the vector, whereby upper bit is taken directly from Rx line.

SHIFT_IN: process(CLK, RESET, SHIFTING, Rx)
variable Buf: std_logic_vector(WIDTH-2 downto 0);
begin

FIFO_IN <= Rx & Buf(WIDTH-2 downto 0);

if Rising_Edge(CLK) and ENABLE = '1' then
if SHIFTING then
Buf := Rx & Buf(WIDTH-2 downto 1);
end if;
end if;

end process;



WIDTH = 1 is not allowed because we get vector(-1 downto 0). Buf should have
length 0 in this case. Compiler sumbles at Rx & Buf(0 downto 1) when
WIDTH=2. The situations like
for I := 0 downto 1 do
are handeled in any general-purpose programming language by not entering
into the loop. What is the proper way to describe the HW in VHDL? The
process must work for WIDTH > 0.

 

[valentin tihomirov]

Thank you very much.