negative hold time

S

skyworld

Guest
Hi,
can anybody explain why there is negative hold time in timing analysis?
I was confused when I am using Design compiler for timing check. Thanks
very much.


skyworld
 
skyworld wrote:
Hi gabor,
thanks for your help. But I am still confused about this. I guess data
must come earlier than rising clock egde so that it can meet setup
time, and the data must be stable after rising clock edge for some time
so that it meets hold time requirement. So I think data must come
earlier than clock and I still confused about your explain. Would you
pls give me a more detailed information? Thanks very much.
Essentially there is a timing window relative to the input clock edge
during which the input data needs to be stable. For the case of
positive
setup and hold times, the clock edge itself is inside this window.

So let's say you have 5 nS setup and 2 nS hold. That means the data
must be stable from 5 nS before the clock edge until 2 nS after the
clock
edge in order to be sampled reliably.

If the hold time is negative, the window does not include the clock
edge. Let's say you have 5 nS setup and -1 nS hold requirements.
That means data must be stable from 5 nS before the clock edge
until 1 nS before the clock edge. This is in fact an easier constraint
to meet. In this case if the active clock edge is rising, and you fed
the same signal to clock and data inputs, you would be guaranteed
to sample the data low. It is possible to use negative hold time
to reduce the clock cycle time by shifting the receiver's clock signal
with respect to the clock of the transmitting source. Normally you
can just regard any negative hold time as zero, since it's unlikely
that your source changes in anticipation of a coming clock edge.

Hope this helps,
Gabor
 
Hi Gabor,
I was also having similar doubts and thanks for your detailed
explanation. But I am not convinced as to how the flip-flop samples the
input data if it has changed, say 1 or 2ns before the clock edge. How
is it taken care of?

Regards,
Srini.

gabor wrote:
skyworld wrote:
Hi gabor,
thanks for your help. But I am still confused about this. I guess data
must come earlier than rising clock egde so that it can meet setup
time, and the data must be stable after rising clock edge for some time
so that it meets hold time requirement. So I think data must come
earlier than clock and I still confused about your explain. Would you
pls give me a more detailed information? Thanks very much.

Essentially there is a timing window relative to the input clock edge
during which the input data needs to be stable. For the case of
positive
setup and hold times, the clock edge itself is inside this window.

So let's say you have 5 nS setup and 2 nS hold. That means the data
must be stable from 5 nS before the clock edge until 2 nS after the
clock
edge in order to be sampled reliably.

If the hold time is negative, the window does not include the clock
edge. Let's say you have 5 nS setup and -1 nS hold requirements.
That means data must be stable from 5 nS before the clock edge
until 1 nS before the clock edge. This is in fact an easier constraint
to meet. In this case if the active clock edge is rising, and you fed
the same signal to clock and data inputs, you would be guaranteed
to sample the data low. It is possible to use negative hold time
to reduce the clock cycle time by shifting the receiver's clock signal
with respect to the clock of the transmitting source. Normally you
can just regard any negative hold time as zero, since it's unlikely
that your source changes in anticipation of a coming clock edge.

Hope this helps,
Gabor
 
Hi gabor,
can I think the negative hold time is used in such case: the delay from
input data pin to internal D flip-flop is large than the delay from
input clk to D clk, so in such case the internal flip-flop 's timing is
within the timing window and has positive setup and hold timing?
thanks.



gabor 写道:

skyworld wrote:
Hi gabor,
thanks for your help. But I am still confused about this. I guess data
must come earlier than rising clock egde so that it can meet setup
time, and the data must be stable after rising clock edge for some time
so that it meets hold time requirement. So I think data must come
earlier than clock and I still confused about your explain. Would you
pls give me a more detailed information? Thanks very much.

Essentially there is a timing window relative to the input clock edge
during which the input data needs to be stable. For the case of
positive
setup and hold times, the clock edge itself is inside this window.

So let's say you have 5 nS setup and 2 nS hold. That means the data
must be stable from 5 nS before the clock edge until 2 nS after the
clock
edge in order to be sampled reliably.

If the hold time is negative, the window does not include the clock
edge. Let's say you have 5 nS setup and -1 nS hold requirements.
That means data must be stable from 5 nS before the clock edge
until 1 nS before the clock edge. This is in fact an easier constraint
to meet. In this case if the active clock edge is rising, and you fed
the same signal to clock and data inputs, you would be guaranteed
to sample the data low. It is possible to use negative hold time
to reduce the clock cycle time by shifting the receiver's clock signal
with respect to the clock of the transmitting source. Normally you
can just regard any negative hold time as zero, since it's unlikely
that your source changes in anticipation of a coming clock edge.

Hope this helps,
Gabor
 
Hi,

Just to add a physical precision.
We can consider that the setup and the hold times are the same in the
most general case. the difference between those timings is just the
timings step used by the analog simulator.
to calculate a setup time for a flip flop, you have a rising (falling)
on D (with the output set to 0(1)) which is fixed and you moved the
clock step by step (a step can be 10ps) up to find the time where the Q
does not store the 1. The setup is the time when the last correct
behaviour occurs.This timing is positive because this is the time
between the rising (falling) data and the clock.

The hold time is exactly the opposite. You calculate the time between
the clock and the data. But it physically the same timing. But it is
negative because you calculate the opposite (clock to data).

I hope i am clear.

Jerome.

skyworld a ĂŠcrit :
Hi gabor,
can I think the negative hold time is used in such case: the delay from
input data pin to internal D flip-flop is large than the delay from
input clk to D clk, so in such case the internal flip-flop 's timing is
within the timing window and has positive setup and hold timing?
thanks.



gabor 写道:

skyworld wrote:
Hi gabor,
thanks for your help. But I am still confused about this. I guess data
must come earlier than rising clock egde so that it can meet setup
time, and the data must be stable after rising clock edge for some time
so that it meets hold time requirement. So I think data must come
earlier than clock and I still confused about your explain. Would you
pls give me a more detailed information? Thanks very much.
Essentially there is a timing window relative to the input clock edge
during which the input data needs to be stable. For the case of
positive
setup and hold times, the clock edge itself is inside this window.

So let's say you have 5 nS setup and 2 nS hold. That means the data
must be stable from 5 nS before the clock edge until 2 nS after the
clock
edge in order to be sampled reliably.

If the hold time is negative, the window does not include the clock
edge. Let's say you have 5 nS setup and -1 nS hold requirements.
That means data must be stable from 5 nS before the clock edge
until 1 nS before the clock edge. This is in fact an easier constraint
to meet. In this case if the active clock edge is rising, and you fed
the same signal to clock and data inputs, you would be guaranteed
to sample the data low. It is possible to use negative hold time
to reduce the clock cycle time by shifting the receiver's clock signal
with respect to the clock of the transmitting source. Normally you
can just regard any negative hold time as zero, since it's unlikely
that your source changes in anticipation of a coming clock edge.

Hope this helps,
Gabor
 
A negative hold time is perfectly reasonable in a system where the
clock to a flip-flop can be guaranteed to have less delay that the
data input path. For example a Xilinx IOB input flip-flop has a delay
element in the data path from the pin to the flip-flop D input. If you
then use a clock path with very low latency, for example by using
a DCM or DLL, you can guarantee that the sampling point on
the data input pin comes some minimum number of nanoseconds
before the rising edge of the clock. This means you could have
some timing margin even if the signal transitions at the same
time as the clock (at the external pin interface, not at the
flip-flop).

skyworld wrote:
Hi,
can anybody explain why there is negative hold time in timing analysis?
I was confused when I am using Design compiler for timing check. Thanks
very much.


skyworld
 
Hi gabor,
thanks for your help. But I am still confused about this. I guess data
must come earlier than rising clock egde so that it can meet setup
time, and the data must be stable after rising clock edge for some time
so that it meets hold time requirement. So I think data must come
earlier than clock and I still confused about your explain. Would you
pls give me a more detailed information? Thanks very much.
 

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