negative hold/setup time ???

[mann!]

hi ,
can anyone please explain how the setup/hold time for a flip flop can
be negative????

also what is maximum frequency of operation of a circuit detemined
wholly by the setup time equation , or are there other factors too?

 

[Harold Ryan]

The setup time is before the clock edge. The hold time is usually the time
that the 'D' input must be held after the clock edge. However, on some logic
families, the 'D' input can be released before the clock edge due to the
internal delay of the flip flop. This would be considered a negative value.

Harold
"mann!" <manan.kathuria@gmail.com> wrote in message
news:1109515596.376804.314280@o13g2000cwo.googlegroups.com...

hi ,
can anyone please explain how the setup/hold time for a flip flop can
be negative????

also what is maximum frequency of operation of a circuit detemined
wholly by the setup time equation , or are there other factors too?