Negation operators synthesis [WIDER_LHS = Negation(NARROWER_

[dm]

Hello, dear All!


Consider following cases with negation, please.

1) Bit-wise
--- 8< ---
module top (in, out);
input [1:0] in;
output [3:0] out;
assign out = ~in; // synthesis tools assign "1" to upper bit (2) of
out
endmodule
--- >8 ---

2) logical
--- 8< ---
module top (in, out);
input [1:0] in;
output [3:0] out;
assign out = !in; // synthesis tools assign "0" to upper bit (2) of
out
endmodule
--- >8 ---

From behavior of synthesis tools, we can see that negation is
synthesized in following way:

- bit width of RHS is changed (filled up with zeroes -- to be the same
as bit width of LHS)
- negation is performed

But I couldn't understand why? Before investigating this fact, I
believed that such behavior is OK only for simulator. What is the
reason for synthesis tool to work in such way -- common practice is to
fill up with zeroes all unused ports.

Any suggestions?


Thanks for the attention and kind regards!
dm

 

[Jonathan Bromley]

On Fri, 26 Oct 2007 10:47:01 -0000, dm <explorer@inbox.ru> wrote:

believed that such behavior is OK only for simulator. What is the
reason for synthesis tool to work in such way

Synthesis has a duty to provide the same behaviour as simulation.
If it cannot do this, it should throw an error. The behaviour
you observed is exactly what you would get from simulation,
and therefore is correct in synthesis.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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